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1. 发明授权

US07243252B2 Synchronization circuit for transferring data using a bus of a different width 有权
标题翻译：使用不同宽度的总线传输数据的同步电路
公开(公告)号：US07243252B2
公开(公告)日：2007-07-10
申请号：US10361620
申请日：2003-02-11
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： H06F7/00 , G06F13/00
CPC分类号： G11C7/10 , G06F13/4018 , G11C7/1045 , G11C7/1051 , G11C7/106 , H03K5/135 , H03M9/00
摘要： A semiconductor device that transmits data in wide bus width regardless of the width of an external data bus connected thereto. On the device's data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L=m/n bits. An output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. A data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
摘要翻译：无论与其连接的外部数据总线的宽度如何，都能以宽的总线宽度传输数据。在器件的数据输出端，m位内部数据被分为n个块。数据选择电路一次选择m / n条数据，数据输出部分将这些数据输出到宽度为L = m / n位的外部数据总线。输出控制电路通过数据选择电路控制数据的选择，同步信号输出部分输出表示所选数据的同步信号。数据输入部分接受通过外部数据总线传送的数据，并且数据获取电路将数据输出到与接受的同步信号输入部分的同步信号相对应的内部数据总线。通过获取对应于所有同步信号的数据，数据获取电路将获得m位数据。

2. 发明授权

US06466491B2 Memory system and memory controller with reliable data latch operation 有权
标题翻译：内存系统和内存控制器具有可靠的数据锁存功能
公开(公告)号：US06466491B2
公开(公告)日：2002-10-15
申请号：US09859489
申请日：2001-05-18
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G06F13/1689 , G11C7/22 , G11C7/222
摘要： A memory controller for controlling a memory that is connected thereto and outputs data of a double data rate together with a strobe signal includes a clock signal generation circuit which generates a clock signal supplied to the memory, and a data acquisition circuit which delays the strobe signal through feedback control that makes a delay substantially equal to a ¼ cycle of the clock signal, and which latches the data in response to a timing signal that is the delayed strobe signal.
摘要翻译：用于控制连接到其上的存储器并与选通信号一起输出双倍数据速率的存储器控制器包括产生提供给存储器的时钟信号的时钟信号产生电路，以及延迟选通信号的数据采集电路通过使得延迟基本上等于时钟信号的1/4周期的反馈控制，并且响应于作为延迟选通信号的定时信号来锁存数据。

3. 发明授权

US08572424B2 Semiconductor device to select and output data to a data bus 有权
标题翻译：半导体器件选择和输出数据到数据总线
公开(公告)号：US08572424B2
公开(公告)日：2013-10-29
申请号：US11806327
申请日：2007-05-31
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G06F13/42
CPC分类号： G11C7/10 , G06F13/4018 , G11C7/1045 , G11C7/1051 , G11C7/106 , H03K5/135 , H03M9/00
摘要： A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
摘要翻译：无论与其连接的外部数据总线的宽度如何，都可以以宽的总线宽度传输数据。在数据输出侧的半导体器件中，m位内部数据被分成n个块。数据选择电路一次选择m / n条数据，数据输出部分将这些数据输出到宽（L =（m / n））位的外部数据总线。此时，输出控制电路通过数据选择电路控制数据的选择，同步信号输出部输出表示所选数据的同步信号。在数据输入侧的半导体装置中，数据输入部接受通过外部数据总线传送的数据，数据获取电路将数据输出到对应于接受的同步信号输入部的同步信号的内部数据总线。通过获取对应于所有同步信号的数据，数据获取电路将获得m位数据。

4. 发明申请

US20070240009A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070240009A1
公开(公告)日：2007-10-11
申请号：US11806327
申请日：2007-05-31
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , G06F13/4018 , G11C7/1045 , G11C7/1051 , G11C7/106 , H03K5/135 , H03M9/00
摘要： A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
摘要翻译：无论与其连接的外部数据总线的宽度如何，都可以以宽的总线宽度传输数据。在数据输出侧的半导体器件中，m位内部数据被分成n个块。数据选择电路一次选择m / n条数据，数据输出部分将这些数据输出到宽（L =（m / n））位的外部数据总线。此时，输出控制电路通过数据选择电路控制数据的选择，同步信号输出部输出表示所选数据的同步信号。在数据输入侧的半导体装置中，数据输入部接受通过外部数据总线传送的数据，数据获取电路将数据输出到对应于接受的同步信号输入部的同步信号的内部数据总线。通过获取对应于所有同步信号的数据，数据获取电路将获得m位数据。

5. 发明授权

US06885571B2 Associative memory having a search bus driving circuit for supplying search data to associative memory cells 失效
标题翻译：关联存储器具有用于向关联存储单元提供搜索数据的搜索总线驱动电路
公开(公告)号：US06885571B2
公开(公告)日：2005-04-26
申请号：US10615910
申请日：2003-07-10
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： A memory cell matrix with a plurality of associative memory cells and match lines are respectively divided into two in the direction of the match line. A first memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the first memory cell matrix, and a match line sense amplifier that detects the potential of the match line. A second memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the second memory cell matrix, a match line sense amplifier that detects the potential of the match line in the second memory cell matrix, and a second match line control circuit. The second match line control circuit operates the match line pre-charge circuit in the second memory cell matrix, to pre-charge the match line, only when the data comparison result in the first memory cell matrix indicates agreement.
摘要翻译：具有多个关联存储器单元和匹配线的存储单元矩阵分别在匹配线的方向上分成两个。第一存储单元矩阵设置有预充电第一存储单元矩阵中的匹配线的匹配线预充电电路和检测匹配线的电位的匹配线读出放大器。第二存储单元矩阵设置有预充电第二存储单元矩阵中的匹配线的匹配线预充电电路，检测第二存储单元矩阵中匹配线的电位的匹配线读出放大器，以及第二匹配线控制电路。第二匹配线控制电路在第二存储单元矩阵中操作匹配线预充电电路，以仅在第一存储单元矩阵中的数据比较结果指示一致时对该匹配线进行预充电。

6. 发明授权

US06560133B2 Content addressable memory device with advanced precharge timing 有权
公开(公告)号：US06560133B2
公开(公告)日：2003-05-06
申请号：US10066628
申请日：2002-02-06
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory device includes a match line having a potential thereof changed according to whether data of a memory cell matches a search key of a search bus, a precharge circuit which precharges the match line, a sample-&-hold circuit which samples and holds the potential of the match line, and a detection circuit which detects the potential held by the sample-&-hold circuit.

7. 发明授权

US06542392B2 Content addressable memory devices determining entry data priority by valid data length 有权
公开(公告)号：US06542392B2
公开(公告)日：2003-04-01
申请号：US10080559
申请日：2002-02-25
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.

8. 发明授权

US06424199B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06424199B1
公开(公告)日：2002-07-23
申请号：US09978022
申请日：2001-10-17
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03K3013
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

9. 发明授权

US5929694A Semiconductor device having voltage generation circuit 失效
标题翻译：具有电压产生电路的半导体装置
公开(公告)号：US5929694A
公开(公告)日：1999-07-27
申请号：US933034
申请日：1997-09-18
申请人： Miki Yanagawa , Yasurou Matsuzaki
发明人： Miki Yanagawa , Yasurou Matsuzaki
IPC分类号： G11C11/413 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/822 , H01L27/04 , H02M3/07 , G05F1/10
CPC分类号： G11C5/143 , G05F3/205 , G11C5/145 , G11C8/08 , H02M3/073
摘要： A semiconductor device operates in one of at least two different modes including a first mode and a second mode. The semiconductor device includes a first voltage generating circuit operating in the first mode and the second mode and having a power to supply a first amount of current in order to generate a predetermined voltage level, and a second voltage generating circuit operating only in the second mode and having a power to supply a second amount of current greater than the first amount of current in order to generate the predetermined voltage level, wherein the first voltage generating circuit increases the first amount of current in the second mode compared to in the first mode.
摘要翻译：半导体器件以包括第一模式和第二模式的至少两种不同模式中的一种工作。半导体器件包括在第一模式和第二模式下工作的第一电压产生电路，并且具有供给第一电流量以产生预定电压电平的功率，以及仅在第二模式中工作的第二电压产生电路并且具有提供大于第一电流量的第二量的电流以产生预定电压电平的电力的功率，其中与第一模式相比，第一电压产生电路增加第二模式中的第一电流量。

10. 发明授权

US06535410B2 Content addressable memory device with reduced power consumption 失效
标题翻译：内容可寻址的存储器件，功耗降低
公开(公告)号：US06535410B2
公开(公告)日：2003-03-18
申请号：US10080561
申请日：2002-02-25
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory device includes a first match line which is a first one of two portions into which a whole match line corresponding to a single item of entry data is divided, and changes from a first potential to a second potential when corresponding entry data does not match an entry key, a second match line which is a second one of the two portions into which the whole match line corresponding to the single item of entry data is divided, and changes from a second potential to a first potential when corresponding entry data does not match an entry key, a first precharge circuit which precharges the first match line to the first potential, a second precharge circuit which precharges the second match line to the second potential, and a short-circuiting circuit which short-circuits the first match line and the second match line with each other prior to precharging by the first and second precharge circuits if both of the first and second match lines indicate a mismatch.
摘要翻译：内容可寻址存储器件包括第一匹配线，其是与单个入口数据项对应的整个匹配线被分割成两部分中的第一匹配线，并且当相应条目数据确定时从第一电位变为第二电位与入口密钥不匹配的第二匹配行，作为对应于单个条目数据项的整个匹配行的两个部分中的第二个匹配行，并且当对应的条目数据从第二个电位变为第一个电位时与第一匹配线预充电到第一电位的第一预充电电路，将第二匹配线预充电到第二电位的第二预充电电路和短路第一匹配的短路电路，如果第一和第二匹配线都表示不匹配，则在由第一和第二预充电电路预充电之前彼此相连。

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