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1. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

2. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

3. 发明申请

US20050242864A1 Semiconductor device, semiconductor system, and digital delay circuit 审中-公开
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US20050242864A1
公开(公告)日：2005-11-03
申请号：US11055784
申请日：2005-02-11
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

4. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

5. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

6. 发明授权

US6049239A Variable delay circuit and semiconductor integrated circuit device 失效
公开(公告)号：US6049239A
公开(公告)日：2000-04-11
申请号：US934783
申请日：1997-09-22
申请人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
发明人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
IPC分类号： G11C11/407 , G06F1/10 , G11C11/4076 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/07 , H03L7/081 , H03L7/087 , H04L7/033 , H04L7/08
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03L7/07 , H03L7/0814 , H03L7/0818 , H03L7/087 , H04L7/033
摘要： A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

7. 发明授权

US06377101B1 Variable delay circuit and semiconductor integrated circuit device 有权
标题翻译：可变延迟电路和半导体集成电路器件
公开(公告)号：US06377101B1
公开(公告)日：2002-04-23
申请号：US09510299
申请日：2000-02-22
申请人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
发明人： Satoshi Eto , Masao Taguchi , Masato Matsumiya , Toshikazu Nakamura , Masato Takita , Mitsuhiro Higashiho , Toru Koga , Hideki Kano , Ayako Kitamoto , Kuninori Kawabata , Koichi Nishimura , Yoshinori Okajima
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/131 , H03K5/133 , H03L7/07 , H03L7/0814 , H03L7/0818 , H03L7/087 , H04L7/033
摘要： A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
摘要翻译：可变延迟电路包括具有第一延迟量的第一栅极和具有大于第一延迟量的第二延迟量的第二栅极。第一延迟量和第二延迟时间之间的差小于第一延迟量。

8. 发明授权

US07941730B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07941730B2
公开(公告)日：2011-05-10
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F11/10 , G06F13/14
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

9. 发明授权

US07417884B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07417884B2
公开(公告)日：2008-08-26
申请号：US11443030
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C5/06 , H04B10/00
CPC分类号： G06F13/4243 , G11C5/066 , G11C7/1006
摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.
摘要翻译：存储器控制器将每个由多个位组成的访问信号复用为光信号并输出复用的光信号。此时，产生根据存储器件波长不同的光信号。存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。存储器接口单元不需要包括用于识别存储器件的解码电路。

10. 发明申请

US20070192527A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070192527A1
公开(公告)日：2007-08-16
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

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