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1. 发明授权

US06333660B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06333660B2
公开(公告)日：2001-12-25
申请号：US09780475
申请日：2001-02-12
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03K3013
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

2. 发明授权

US06525587B2 Semiconductor integrated circuit device including a clock synchronous type logical processing circuit 失效
标题翻译：包括时钟同步型逻辑处理电路的半导体集成电路器件
公开(公告)号：US06525587B2
公开(公告)日：2003-02-25
申请号：US10086874
申请日：2002-03-04
申请人： Hiroshi Makino
发明人： Hiroshi Makino
IPC分类号： H03K3013
CPC分类号： G06F1/10
摘要： A first circuit group for generating a dock signal, and a second circuit group for carrying out a transferring operation and a logical processing operation on a signal in accordance with this clock signal are arranged, and operation voltage sources of these circuit groups are made individually settable. Thus, the operation speeds of the first circuit group and the second circuit group are individually adjusted so as to eliminate a problem of an erroneous operation due to a racing through an operation. An erroneous operation due to a racing caused by dock skew can be reliably prevented through an external operation.
摘要翻译：布置了用于产生停靠信号的第一电路组和用于对根据该时钟信号的信号执行转移操作和逻辑处理操作的第二电路组，并且使这些电路组的工作电压源单独设置。因此，分别调整第一电路组和第二电路组的操作速度，从而消除由于通过操作的竞赛而导致的错误操作的问题。可以通过外部操作可靠地防止由于由歪斜引起的赛车引起的错误操作。

3. 发明授权

US06236252B1 Low-noise current pulse generator device 有权
标题翻译：低噪声电流脉冲发生器
公开(公告)号：US06236252B1
公开(公告)日：2001-05-22
申请号：US09236114
申请日：1999-01-25
申请人： Pierre Genest , Fuji Yang
发明人： Pierre Genest , Fuji Yang
IPC分类号： H03K3013
CPC分类号： G05F3/262
摘要： A current pulse generator device includes current pulse generator circuits and polarizer circuits. It further includes holding circuits for holding the polarization voltage connected to the generator circuits, the holding circuits connected via switch circuits to the polarizer circuits. The switch circuits can assume in succession a closed or adjustment position in which they connect the holding circuits to the polarizer circuits, and an open or operating position in which they isolate the holding circuits from the polarizer circuits so that the generator circuits generate at least one low-noise current pulse. The device can be used in a phase comparator and a radiocommunication terminal, and the phase comparator can be used in a synthesiser.
摘要翻译：电流脉冲发生器装置包括电流脉冲发生器电路和偏振器电路。它还包括用于保持连接到发生器电路的极化电压的保持电路，通过开关电路连接到偏振器电路的保持电路。开关电路可以连续地假设闭合或调节位置，在该位置，它们将保持电路连接到偏振器电路以及将保持电路与偏振器电路隔离开的或工作位置，使得发生器电路产生至少一个低噪声电流脉冲。该器件可用于相位比较器和无线电通信终端，相位比较器可用于合成器。

4. 发明授权

US06724232B1 Dual tristate path output buffer control 有权
标题翻译：双路三通路输出缓冲控制
公开(公告)号：US06724232B1
公开(公告)日：2004-04-20
申请号：US10353375
申请日：2003-01-29
申请人： Jonathan F. Churchill
发明人： Jonathan F. Churchill
IPC分类号： H03K3013
CPC分类号： H03K19/09429
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于（i）时钟信号和（ii）一个或多个第二控制信号而产生一个或多个第一控制信号。第二电路可以（i）经由一个或多个路径电路耦合到第一电路，并且（ii）被配置为响应于一个或多个第一控制信号呈现输出信号。所有一个或多个第一控制信号可能具有优选的边缘偏斜。

5. 发明授权

US06192027B1 Apparatus, system, and method for dual-active fibre channel loop resiliency during controller failure 有权
标题翻译：控制器故障期间双主动光纤通道环路弹性的装置，系统和方法
公开(公告)号：US06192027B1
公开(公告)日：2001-02-20
申请号：US09146825
申请日：1998-09-04
申请人： Mohamad El-Batal
发明人： Mohamad El-Batal
IPC分类号： H03K3013
CPC分类号： G06F11/2089 , G06F11/2007 , G06F11/2015
摘要： This invention relates generally to Fibre Channel Loop topology in a computer system and more particularly to structure and method for by-passing a failed controller connected in a dual-active mode Fibre Channel Loop.
摘要翻译：本发明一般涉及计算机系统中的光纤通道环路拓扑，更具体地涉及用于旁路连接在双活动模式光纤通道环路中的故障控制器的结构和方法。

6. 发明授权

US06545508B2 Detection of clock signal period abnormalities 失效
公开(公告)号：US06545508B2
公开(公告)日：2003-04-08
申请号：US10066508
申请日：2002-01-31
申请人： Hisanori Senba
发明人： Hisanori Senba
IPC分类号： H03K3013
CPC分类号： G01R31/31727 , H03K5/159 , H03K5/19
摘要： A clock monitoring circuit is disclosed for detecting that the period of a clock signal has become shorter than a predetermined time interval. The clock monitoring monitoring circuit comprises a first and second flip-flop circuits that are D-type flip-flops, a delay circuit, and a gate circuit. The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time interval by the delay circuit and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay circuit is set to be equal to the previously described predetermined period. The gate circuit receives the output signals of the first and second flip-flop circuits, and provides a signal whose logic level when the period of the received clock signal is the predetermined period differs from that when it is shorter than the predetermined period. The fact that the period of the clock signal has become shorter than the predetermined period can thus be detected.

7. 发明授权

US06424199B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06424199B1
公开(公告)日：2002-07-23
申请号：US09978022
申请日：2001-10-17
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03K3013
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

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