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1. 发明授权

US06424199B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06424199B1
公开(公告)日：2002-07-23
申请号：US09978022
申请日：2001-10-17
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03K3013
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

2. 发明授权

US5929694A Semiconductor device having voltage generation circuit 失效
标题翻译：具有电压产生电路的半导体装置
公开(公告)号：US5929694A
公开(公告)日：1999-07-27
申请号：US933034
申请日：1997-09-18
申请人： Miki Yanagawa , Yasurou Matsuzaki
发明人： Miki Yanagawa , Yasurou Matsuzaki
IPC分类号： G11C11/413 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/822 , H01L27/04 , H02M3/07 , G05F1/10
CPC分类号： G11C5/143 , G05F3/205 , G11C5/145 , G11C8/08 , H02M3/073
摘要： A semiconductor device operates in one of at least two different modes including a first mode and a second mode. The semiconductor device includes a first voltage generating circuit operating in the first mode and the second mode and having a power to supply a first amount of current in order to generate a predetermined voltage level, and a second voltage generating circuit operating only in the second mode and having a power to supply a second amount of current greater than the first amount of current in order to generate the predetermined voltage level, wherein the first voltage generating circuit increases the first amount of current in the second mode compared to in the first mode.
摘要翻译：半导体器件以包括第一模式和第二模式的至少两种不同模式中的一种工作。半导体器件包括在第一模式和第二模式下工作的第一电压产生电路，并且具有供给第一电流量以产生预定电压电平的功率，以及仅在第二模式中工作的第二电压产生电路并且具有提供大于第一电流量的第二量的电流以产生预定电压电平的电力的功率，其中与第一模式相比，第一电压产生电路增加第二模式中的第一电流量。

3. 发明授权

US06509763B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06509763B2
公开(公告)日：2003-01-21
申请号：US10162565
申请日：2002-06-06
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G01R1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

4. 发明授权

US06225841B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06225841B1
公开(公告)日：2001-05-01
申请号：US09556948
申请日：2000-04-21
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03B1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

5. 发明授权

US6104225A Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译：半导体器件采用互补时钟和信号输入状态检测电路相同
公开(公告)号：US6104225A
公开(公告)日：2000-08-15
申请号：US76810
申请日：1998-05-13
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G11C7/22 , H03K5/00 , H03K5/135 , H03K5/151 , H03L7/081 , G06F1/04
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
摘要翻译：公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟，根据第二外部时钟状态检测电路的判断。

6. 发明申请

US20080285375A1 SEMICONDUCTOR DEVICE, MODULE INCLUDING THE SEMICONDUCTOR DEVICE, AND SYSTEM INCLUDING THE MODULE 审中-公开
标题翻译：半导体器件，包括半导体器件的模块和包括模块的系统
公开(公告)号：US20080285375A1
公开(公告)日：2008-11-20
申请号：US12124765
申请日：2008-05-21
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C8/18 , H03L7/00
CPC分类号： G11C7/1057 , G06F1/10 , G06F5/06 , G11C5/063 , G11C7/1051 , G11C7/22 , G11C7/222 , H03L7/07 , H03L7/081
摘要： A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.
摘要翻译：模块包括半导体器件，产生第二时钟的相位调整电路，使得从半导体器件输出的相位调整信号和第一时钟具有预定的相位关系，以及设置在半导体器件中的输出电路，来自第二个时钟的相位调整信号。

7. 发明授权

US07345942B2 Memory circuit with automatic refresh function 有权
标题翻译：内存电路具有自动刷新功能
公开(公告)号：US07345942B2
公开(公告)日：2008-03-18
申请号：US11413204
申请日：2006-04-28
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.
摘要翻译：根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令在规定的刷新周期内部。并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制。根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。

8. 发明申请

US20070206431A1 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 审中-公开
标题翻译：具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件
公开(公告)号：US20070206431A1
公开(公告)日：2007-09-06
申请号：US11790834
申请日：2007-04-27
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C11/4072
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be interrupted among the external command operations.
摘要翻译：根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令在规定的刷新周期内部。并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制。根据本发明，当产生刷新定时信号时，可以在外部命令操作之间中断刷新操作。

9. 发明授权

US07154799B2 Semiconductor memory with single cell and twin cell refreshing 有权
标题翻译：半导体存储器与单细胞和双胞胎清爽
公开(公告)号：US07154799B2
公开(公告)日：2006-12-26
申请号：US11098557
申请日：2005-04-05
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4067
摘要： Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.
摘要翻译：标志分别形成为分别对应于包括易失性存储单元的存储单元组。每个标志指示存储器单元将数据存储在第二存储器模式中的设置状态。在从每个存储器单元独立地保持数据的第一存储器模式改变为在每个存储单元组的存储单元中保留相同数据的第二存储器模式的改变操作中，每个标志响应于首先访问相应的存储单元组。因此，在每个存储单元组中仅在第二存储器模式中进行第一次访问。存储单元按照改变操作中的标志在模式下访问，从而即使在改变操作期间也允许管理半导体存储器的系统自由地访问存储单元。因此，可以消除实际的改变时间。

10. 发明授权

US07120761B2 Multi-port memory based on DRAM core 有权
公开(公告)号：US07120761B2
公开(公告)日：2006-10-10
申请号：US10284092
申请日：2002-10-31
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F12/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

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