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1. 发明授权

US06791083B2 Image compensation device for a scanning electron microscope 有权
标题翻译：用于扫描电子显微镜的图像补偿装置
公开(公告)号：US06791083B2
公开(公告)日：2004-09-14
申请号：US10207551
申请日：2002-07-29
申请人： Kevin Chan Ee Peng , Yelehanka Ramachandramurthy Pradeep , Chua Thow Phock
发明人： Kevin Chan Ee Peng , Yelehanka Ramachandramurthy Pradeep , Chua Thow Phock
IPC分类号： G01N2300
CPC分类号： H01J37/09 , H01J2237/28
摘要： An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electro-magnetic emissions generating by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.
摘要翻译：一种用于在由相邻制造设备产生的外部电磁发射的影响下由SEM形成的临界尺寸线图像的变形的装置。外部发射导致高三西格玛A / C分量。校正装置包括安装在扫描电镜的柱壳体上的外部屏蔽线圈。控制发光驱动器安装到外部屏蔽线圈，其中具有变压器的可变分压器具有可变电阻器。调节可变电阻器改变A / C信号的正弦波的振幅，从而控制电发射驱动器，同时减少三西格玛A / C分量的影响。

2. 发明申请

US20090108257A1 CRITICAL DIMENSION FOR TRENCH AND VIAS 有权
标题翻译： TRENCH和VIAS的关键尺寸
公开(公告)号：US20090108257A1
公开(公告)日：2009-04-30
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

3. 发明授权

US06726545B2 Linear polishing for improving substrate uniformity 失效
标题翻译：线性抛光，提高基体均匀性
公开(公告)号：US06726545B2
公开(公告)日：2004-04-27
申请号：US10134821
申请日：2002-04-26
申请人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B100
CPC分类号： B24B37/16 , B24B21/10 , B24B37/245
摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
摘要翻译：一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。每个带具有外部抛光表面和内部光滑表面。皮带沿着彼此间隔开，在每一端共享公共轴线。皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。压板构件插入每个带并且放置在成对的辊之间。压板提供抛光平面和抛光带的支撑表面。抛光平面包括与平面下方的细长的增压室连通的多个孔。该室供应压缩气体以向抛光带施加向上的压力。驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

4. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

5. 发明授权

US06455377B1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
标题翻译：通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法
公开(公告)号：US06455377B1
公开(公告)日：2002-09-24
申请号：US09765040
申请日：2001-01-19
申请人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
摘要翻译：一种制造垂直沟道晶体管的方法，包括以下步骤。提供具有上表面的半导体衬底。在半导体衬底上形成高掺杂N型下部外延硅层。在下部外延硅层上形成低掺杂P型中间外延硅层。在中间外延硅层上形成高掺杂N型上部外延硅层。蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。在隔离槽内形成氧化物。氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。栅极导体层形成在栅极电介质层上，填充栅极沟槽。

6. 发明授权

US06440800B1 Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers 失效
公开(公告)号：US06440800B1
公开(公告)日：2002-08-27
申请号：US09769814
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/365 , H01L29/7827
摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

7. 发明授权

US06399448B1 Method for forming dual gate oxide 失效
标题翻译：形成双栅极氧化物的方法
公开(公告)号：US06399448B1
公开(公告)日：2002-06-04
申请号：US09443426
申请日：1999-11-19
申请人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.
摘要翻译：一种在半导体衬底的第二区域被掩蔽的同时，在半导体衬底的第一区域中注入氮离子形成多层栅极氧化层的方法; 在半导体衬底的第一区域被掩蔽时将氩离子注入到半导体衬底的第二区域中; 并且热生长栅极氧化物层，其中氧化物生长在第一区域中延迟并在第二区域增强。在使用与用于低电压栅极的氮注入相同的注入掩模的氮掺杂之前，以及在使用相同植入物的氩注入之前，可以可选地将阈值电压注入和/或抗穿透注入注入到半导体衬底中掩模作为高压栅极的氩离子注入，进一步减少加工步骤。

8. 发明授权

US06316304B1 Method of forming spacers of multiple widths 有权
标题翻译：形成多个宽度的间隔物的方法
公开(公告)号：US06316304B1
公开(公告)日：2001-11-13
申请号：US09614553
申请日：2000-07-12
申请人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Tjin Tjin Tjoa , Kelvin Wei Loong Loh
发明人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Tjin Tjin Tjoa , Kelvin Wei Loong Loh
IPC分类号： H01L218238
CPC分类号： H01L21/8238 , H01L21/823468
摘要： A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.
摘要翻译：描述了形成具有不同宽度的栅极侧壁间隔物的方法。间隔宽度的变化允许通过改变轻掺杂源极/漏极延伸部分的尺寸来优化MOSFET特性。该方法使用其中通过常规技术在衬底上形成包括栅电极和栅极氧化物的栅极结构的方法来实现。轻掺杂的源极漏极延伸部被注入到不被栅极结构保护的衬底中。然后用绝缘衬垫层覆盖暴露的衬底和栅极结构。之后是绝缘衬垫层上的蚀刻停止层沉积。然后在蚀刻停止层上沉积第一间隔氧化物层。掩蔽需要较厚间隔物的区域，并且去除未掩蔽的间隔氧化物层。然后剥去掩模，并在整个表面上生长附加的间隔氧化物。结果是在先前蚀刻步骤期间由掩模保护的区域中较厚的氧化物。氧化物被各向异性蚀刻，并且沿着栅极侧壁形成间隔物。在具有较厚氧化物的区域中，间隔物较宽。该过程通过蚀刻不被间隔物保护的蚀刻停止层而继续。然后通过将离子注入到不被栅极结构和侧壁间隔物保护的衬底中来形成源极和漏极。通过调整蚀刻停止层和间隔氧化物层的总厚度来实现间隔物宽度的调整。通过改变第一间隔氧化物层的沉积厚度来控制间隔宽度变化。

9. 发明授权

US06281093B1 Method to reduce trench cone formation in the fabrication of shallow trench isolations 失效
标题翻译：在浅沟槽隔离制造中减少沟槽形成的方法
公开(公告)号：US06281093B1
公开(公告)日：2001-08-28
申请号：US09619016
申请日：2000-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Qinghua Zhong , Zheng Zou , Henry Gerung
发明人： Yelehanka Ramachandramurthy Pradeep , Qinghua Zhong , Zheng Zou , Henry Gerung
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/76224
摘要： A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
摘要翻译：已经实现了制造浅沟槽隔离的新方法。在半导体衬底上形成二氧化硅层。沉积氮化硅层覆盖二氧化硅层。图案化氮化硅层以暴露其中规划浅沟槽隔离的半导体衬底。将离子注入到暴露的半导体衬底中。植入损伤覆盖半导体衬底的任何被动表面材料。暴露的半导体衬底被蚀刻以形成沟槽。在蚀刻期间，损坏的被动表面材料被去除，从而防止形成沟槽。沉积沟槽填充层以填充沟槽。在集成电路器件的制造中，沟槽填充层被抛光以完成浅沟槽隔离。

10. 发明授权

US06228770B1 Method to form self-sealing air gaps between metal interconnects 有权
标题翻译：在金属互连之间形成自密封气隙的方法
公开(公告)号：US06228770B1
公开(公告)日：2001-05-08
申请号：US09531784
申请日：2000-03-21
申请人： Yelehanka Ramachandramurthy Pradeep , Vijai Kumar Chhagan , Henry Gerung , Madhusudan Mukhopadhyay
发明人： Yelehanka Ramachandramurthy Pradeep , Vijai Kumar Chhagan , Henry Gerung , Madhusudan Mukhopadhyay
IPC分类号： H01L2100
CPC分类号： H01L21/7682
摘要： A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.
摘要翻译：实现了在制造集成电路器件中在相邻互连之间形成具有气隙的金属互连的新方法。提供半导体衬底。金属互连形成在半导体衬底上。沉积氮化硅衬垫层。沉积间隙填充氧化物层以填充相邻的金属互连之间的间隙。间隙填充氧化物层被抛光到氮化硅衬垫层。沉积氮化硅薄层。使用金属互连的过大的反向掩模来对氮化硅薄层进行构图。氮化硅薄层的图案化形成开口，从而暴露间隙填充氧化物的一部分。间隙填充氧化物层被蚀刻掉。沉积氮化硅薄层和氮化硅衬层的自密封氧化层。自密封氧化物层在氮化硅薄层和氮化硅衬垫层之间的间隙上密封，从而在相邻的金属互连之间形成永久的气隙，并且完成集成电路。

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