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1. 发明申请

US20090108257A1 CRITICAL DIMENSION FOR TRENCH AND VIAS 有权
标题翻译： TRENCH和VIAS的关键尺寸
公开(公告)号：US20090108257A1
公开(公告)日：2009-04-30
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

2. 发明授权

US08293545B2 Critical dimension for trench and vias 有权
标题翻译：沟槽和通孔的关键尺寸
公开(公告)号：US08293545B2
公开(公告)日：2012-10-23
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan Shan Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan Shan Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： G01R31/26 , H01L21/66 , H01L23/58 , H01L29/10
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

3. 发明授权

US08354347B2 Method of forming high-k dielectric stop layer for contact hole opening 有权
公开(公告)号：US08354347B2
公开(公告)日：2013-01-15
申请号：US11953881
申请日：2007-12-11
申请人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/461
CPC分类号： H01L21/76832 , H01L21/76895 , H01L21/76897
摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

4. 发明授权

US06350661B2 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06350661B2
公开(公告)日：2002-02-26
申请号：US09882682
申请日：2001-06-18
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

5. 发明申请

US20090250818A1 VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE 有权
标题翻译：通过改变通过底部几何轮廓的电力改进
公开(公告)号：US20090250818A1
公开(公告)日：2009-10-08
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

6. 发明授权

US07352064B2 Multiple layer resist scheme implementing etch recipe particular to each layer 有权
标题翻译：多层抗蚀剂方案实现每层特有的蚀刻配方
公开(公告)号：US07352064B2
公开(公告)日：2008-04-01
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
发明人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

7. 发明授权

US06297126B1 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06297126B1
公开(公告)日：2001-10-02
申请号：US09351240
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

8. 发明授权

US06228727B1 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess 有权
标题翻译：形成具有圆角和减少的沟槽氧化物凹陷的浅沟槽隔离的方法
公开(公告)号：US06228727B1
公开(公告)日：2001-05-08
申请号：US09405061
申请日：1999-09-27
申请人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
IPC分类号： H01L21336
CPC分类号： H01L21/3086 , H01L21/31053 , H01L21/31612 , H01L21/32 , H01L21/76232
摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.
摘要翻译：已经实现了制造浅沟槽隔离的方法。提供半导体衬底。生长覆盖半导体衬底的焊盘氧化物层。沉积氮化硅层。将氮化硅层和焊盘氧化物层图案化以形成硬掩模。硬掩模中的开口对应于半导体衬底中的规划沟槽。沉积氮化硅层和半导体衬底上的二氧化硅层。二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。蚀刻半导体衬底以形成沟槽。蚀刻掉侧壁间隔物。对半导体衬底进行溅射蚀刻以使沟槽的角落四周。生长在半导体衬底上的氧化物沟槽衬里层。沉积氮化硅层并填充沟槽的沟槽填充层。沟槽填充层被抛光到氮化硅层的顶表面。蚀刻掉氮化硅层。沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

9. 发明授权

US07781895B2 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US07781895B2
公开(公告)日：2010-08-24
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

10. 发明授权

US07691739B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07691739B2
公开(公告)日：2010-04-06
申请号：US11374848
申请日：2006-03-13
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

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