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1. 发明授权

US06726545B2 Linear polishing for improving substrate uniformity 失效
标题翻译：线性抛光，提高基体均匀性
公开(公告)号：US06726545B2
公开(公告)日：2004-04-27
申请号：US10134821
申请日：2002-04-26
申请人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B100
CPC分类号： B24B37/16 , B24B21/10 , B24B37/245
摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
摘要翻译：一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。每个带具有外部抛光表面和内部光滑表面。皮带沿着彼此间隔开，在每一端共享公共轴线。皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。压板构件插入每个带并且放置在成对的辊之间。压板提供抛光平面和抛光带的支撑表面。抛光平面包括与平面下方的细长的增压室连通的多个孔。该室供应压缩气体以向抛光带施加向上的压力。驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

2. 发明授权

US06248006B1 CMP uniformity 失效
标题翻译： CMP均匀性
公开(公告)号：US06248006B1
公开(公告)日：2001-06-19
申请号：US09490155
申请日：2000-01-24
申请人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B508
CPC分类号： B24B37/20 , B24B37/26 , B24B57/02
摘要： A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.
摘要翻译：提供了允许半导体表面的均匀抛光的新设备。传统CMP方法的单个抛光垫被分成分裂垫，分离垫允许跨晶片表面的CMP控制参数的单独调整。这些调整可以从晶片的中心延伸到其周边（沿着晶片的半径），从而可以消除抛光表面的中心与表面周边之间的抛光不均匀的常规问题那是抛光。

3. 发明授权

US06284613B1 Method for forming a T-gate for better salicidation 有权
标题翻译：用于形成更好的盐析的T型门的方法
公开(公告)号：US06284613B1
公开(公告)日：2001-09-04
申请号：US09434920
申请日：1999-11-05
申请人： Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep , Ramakrishnan Rajagopal
发明人： Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep , Ramakrishnan Rajagopal
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/42376 , H01L29/66545 , H01L29/7833 , H01L29/7836
摘要： A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.
摘要翻译：一种用于T栅极和自对准硅化物工艺的方法，其允许窄的底栅宽度低于0.25μm和宽的顶栅宽度以允许在T栅极的顶部上的硅化物栅极接触。在衬底上形成由绝缘材料构成的虚拟栅极。然后，使用伪栅极作为掩模，优选通过将f（I / I）杂质离子注入到衬底中来形成与虚拟栅极相邻的LDD区域。在衬底表面上形成衬垫氧化物层和电介质层。虚拟栅极上的电介质层优选地通过CMP工艺去除。然后我们去除虚拟栅极以形成露出衬底表面的栅极开口。在栅极开口中的衬底表面上形成栅极电介质层。我们在电介质层和栅极开口中的衬底表面上形成多晶硅层。图案化多晶硅层以形成T形栅极。去除电介质层。我们通过离子注入工艺形成与T型栅极相邻的源极/漏极（S / D）区域。在T栅极和衬底之上形成硅化物层，以形成与SID区的硅化物接触和到T栅极的栅极接触。然后我们在T栅极和衬底上形成介电层（ILD）。我们通过介电层形成接触开口以暴露S / D区域和T型栅极。我们与S / D区域和T型门形成联系。

4. 发明授权

US06399448B1 Method for forming dual gate oxide 失效
标题翻译：形成双栅极氧化物的方法
公开(公告)号：US06399448B1
公开(公告)日：2002-06-04
申请号：US09443426
申请日：1999-11-19
申请人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.
摘要翻译：一种在半导体衬底的第二区域被掩蔽的同时，在半导体衬底的第一区域中注入氮离子形成多层栅极氧化层的方法; 在半导体衬底的第一区域被掩蔽时将氩离子注入到半导体衬底的第二区域中; 并且热生长栅极氧化物层，其中氧化物生长在第一区域中延迟并在第二区域增强。在使用与用于低电压栅极的氮注入相同的注入掩模的氮掺杂之前，以及在使用相同植入物的氩注入之前，可以可选地将阈值电压注入和/或抗穿透注入注入到半导体衬底中掩模作为高压栅极的氩离子注入，进一步减少加工步骤。

5. 发明授权

US06337262B1 Self aligned T-top gate process integration 有权
标题翻译：自对准T顶门工艺集成
公开(公告)号：US06337262B1
公开(公告)日：2002-01-08
申请号：US09519611
申请日：2000-03-06
申请人： Yelehanka Ramachandramurthy Pradeep , Chivukula Subrahmanyam , Vijai Kumar Chhagan , Henry Gerung
发明人： Yelehanka Ramachandramurthy Pradeep , Chivukula Subrahmanyam , Vijai Kumar Chhagan , Henry Gerung
IPC分类号： H01L2128
CPC分类号： H01L29/66583 , H01L21/28114 , H01L29/66553
摘要： A new method is provided for the integration of the of T-top gate process. Active regions are defined and bounded by STI's on the surface of a substrate. The pad oxide is removed from the substrate and replaced by a layer of SAC oxide. A thin layer of nitride is deposited that covers the surface of the created layer of SAC oxide and the surface of the STI regions. A layer of TEOS is deposited and etched defining the regions where the gate electrodes need to be formed. Gate spacers are next formed on the sidewalls of the openings that have been created in the layer of TEOS. The required implants (such as channel implant and threshold implant) are performed, the gate structure is then grown in the openings that have been created in the layer of TEOS. After the gate structure has been completed, the surface of the created structure is polished and the remaining layer of TEOS is removed. Source and drain regions implants can now be performed, LDD regions are implanted using a tilted implant. This tilted implant penetrates underneath the body of the created gate structures thereby creating the LDD regions. The removal of the layer of TEOS leaves in place the gate structures, one such structure is located in the active region of the surface of the substrate, two additional structures that have been created on the surface of the STI regions.
摘要翻译：提供了一种用于集成T-top门过程的新方法。有源区域由衬底表面上的STI限定和界定。衬垫氧化物从衬底上去除并被一层SAC氧化物代替。沉积薄层的氮化物，其覆盖所形成的SAC氧化物层的表面和STI区域的表面。沉积和蚀刻一层TEOS，限定需要形成栅电极的区域。接下来，在已经在TEOS层中形成的开口的侧壁上形成栅极间隔物。执行所需的植入物（例如通道植入和阈值植入），然后在已经在TEOS层中产生的开口中生长栅极结构。在栅极结构完成之后，对所形成的结构的表面进行抛光并除去TEOS的剩余层。现在可以执行源极和漏极区域植入，使用倾斜植入物植入LDD区域。这种倾斜的植入物渗透在所产生的栅极结构的主体下面，从而形成LDD区域。 TEOS层的去除留下了栅极结构，一个这样的结构位于衬底的表面的有源区域中，在STI区域的表面上产生了两个另外的结构。

6. 发明授权

US5747369A Formation of a capacitor using a sacrificial etch stop 失效
标题翻译：使用牺牲蚀刻停止形成电容器
公开(公告)号：US5747369A
公开(公告)日：1998-05-05
申请号：US782706
申请日：1997-01-13
申请人： Arjun Kumar Kantimahanti , Chivukula Subrahmanyam , Mei Sheng Zhou
发明人： Arjun Kumar Kantimahanti , Chivukula Subrahmanyam , Mei Sheng Zhou
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8242
CPC分类号： H01L28/40 , H01L27/0629
摘要： A method is described for forming capacitors in integrated circuits by making the capacitors concurrently with the fabrication of the interconnection wiring levels. A single additional photolithographic step and two depositions are required to form capacitors within each wiring level. A key feature of the invention is the use of an etch-stop to protect the capacitor dielectric during contact or via etching. The storage plates of the capacitor are formed from two successive conductor levels which can include polysilicon levels as well. The process is particularly suited to the manufacture of logic circuits and can be used effectively in MOSFET, bipolar and BiCMOS processes.
摘要翻译：描述了一种用于在集成电路中形成电容器的方法，其中通过在制造互连线路电平的同时使电容器同时进行。需要单个附加的光刻步骤和两个沉积以在每个布线层内形成电容器。本发明的一个关键特征是在接触或通过蚀刻期间使用蚀刻停止来保护电容器电介质。电容器的存储板由两个连续的导体电平形成，也可以包括多晶硅层。该过程特别适用于逻辑电路的制造，可以有效地用于MOSFET，双极和BiCMOS工艺。

7. 发明授权

US06689653B1 Method of preserving the top oxide of an ONO dielectric layer via use of a capping material 有权
标题翻译：通过使用封盖材料来保存ONO电介质层的顶部氧化物的方法
公开(公告)号：US06689653B1
公开(公告)日：2004-02-10
申请号：US10464255
申请日：2003-06-18
申请人： Xavier Teo Leng Seah , Chivukula Subrahmanyam , Rajan Rajgopal
发明人： Xavier Teo Leng Seah , Chivukula Subrahmanyam , Rajan Rajgopal
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： Methods of protecting, and increasing the thickness of, the oxidized silicon nitride (ON), component of an oxidized silicon nitride on silicon oxide (ONO), layer of a non-volatile memory device, during the hydrofluoric (HF), acid type procedures used for peripheral devices simultaneously fabricated with the non-volatile memory device, has been developed. A first method features a silicon nitride layer located only overlying the ONO layer of the non-volatile memory device, formed prior to HF type pre-clean procedures performed prior to gate oxidation procedures used for peripheral devices. After the gate oxidation procedures the silicon nitride capping layer is selectively removed. A second method features a polysilicon capping layer again located only overlying the ONO layer of the non-volatile memory device, again formed prior to HF type pre-clean procedures. For this iteration the protective polysilicon capping layer is oxidized during subsequent gate oxidation procedures and adds onto the ONO layer, subsequently overlaid by a control gate structure of the non-volatile memory device.
摘要翻译：在氢氟酸（HF）酸型程序期间，氧化氮化硅（ON），氧化硅氮化物在氧化硅（ONO）的组分，非易失性存储器件的层上的保护和增加厚度的方法用于与非易失性存储器件同时制造的外围设备。第一种方法的特征在于位于仅覆盖在非易失性存储器件的ONO层上的氮化硅层，其在用于外围器件的栅极氧化程序之前执行的HF型预清洁程序之前形成。在栅极氧化步骤之后，选择性地去除氮化硅覆盖层。第二种方法的特征在于再次位于非易失性存储器件的ONO层上的多晶硅覆盖层，再次形成在HF型预清洁程序之前。对于该迭代，保护性多晶硅覆盖层在随后的栅极氧化过程中被氧化，并且添加到ONO层上，随后由非易失性存储器件的控制栅极结构覆盖。

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