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1. 发明授权

US06316304B1 Method of forming spacers of multiple widths 有权
标题翻译：形成多个宽度的间隔物的方法
公开(公告)号：US06316304B1
公开(公告)日：2001-11-13
申请号：US09614553
申请日：2000-07-12
申请人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Tjin Tjin Tjoa , Kelvin Wei Loong Loh
发明人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Tjin Tjin Tjoa , Kelvin Wei Loong Loh
IPC分类号： H01L218238
CPC分类号： H01L21/8238 , H01L21/823468
摘要： A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.
摘要翻译：描述了形成具有不同宽度的栅极侧壁间隔物的方法。间隔宽度的变化允许通过改变轻掺杂源极/漏极延伸部分的尺寸来优化MOSFET特性。该方法使用其中通过常规技术在衬底上形成包括栅电极和栅极氧化物的栅极结构的方法来实现。轻掺杂的源极漏极延伸部被注入到不被栅极结构保护的衬底中。然后用绝缘衬垫层覆盖暴露的衬底和栅极结构。之后是绝缘衬垫层上的蚀刻停止层沉积。然后在蚀刻停止层上沉积第一间隔氧化物层。掩蔽需要较厚间隔物的区域，并且去除未掩蔽的间隔氧化物层。然后剥去掩模，并在整个表面上生长附加的间隔氧化物。结果是在先前蚀刻步骤期间由掩模保护的区域中较厚的氧化物。氧化物被各向异性蚀刻，并且沿着栅极侧壁形成间隔物。在具有较厚氧化物的区域中，间隔物较宽。该过程通过蚀刻不被间隔物保护的蚀刻停止层而继续。然后通过将离子注入到不被栅极结构和侧壁间隔物保护的衬底中来形成源极和漏极。通过调整蚀刻停止层和间隔氧化物层的总厚度来实现间隔物宽度的调整。通过改变第一间隔氧化物层的沉积厚度来控制间隔宽度变化。

2. 发明授权

US07541234B2 Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas 有权
标题翻译：通过同时去除不同有源区上的光致抗蚀剂层和含碳层来制造集成电路晶体管的方法
公开(公告)号：US07541234B2
公开(公告)日：2009-06-02
申请号：US11266024
申请日：2005-11-03
申请人： Chong Kwang Chang , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra , O Sung Kwon , Tjin Tjin Tjoa , Young Gun Ko
发明人： Chong Kwang Chang , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra , O Sung Kwon , Tjin Tjin Tjoa , Young Gun Ko
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.
摘要翻译：集成电路晶体管可以通过在集成电路基板的第一有源区域和集成电路基板的第二有源区域上的含碳层同时去除光致抗蚀剂层来制造，以在第二层上露出氮化物应力产生层活动区域。可以使用单个掩模来限定用于去除第一有源区域上的光致抗蚀剂层的第二有源区域和用于将源极/漏极区域注入到第二有源区域中。

3. 发明授权

US06277716B1 Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system 失效
标题翻译：通过使用具有可预测的过早端点系统的多步骤蚀刻工艺来减少栅极氧化物损伤的方法
公开(公告)号：US06277716B1
公开(公告)日：2001-08-21
申请号：US09425908
申请日：1999-10-25
申请人： Vijaikumar Chhagan , Yelehanka R. Pradeep , Tjin Tjin Tjoa
发明人： Vijaikumar Chhagan , Yelehanka R. Pradeep , Tjin Tjin Tjoa
IPC分类号： H01L214763
CPC分类号： H01L21/32137
摘要： A method of fabricating a gate stack having an endpoint detect layer and a multi-step etch process to prevent damage to a gate dielectric layer. The special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon to oxide ratio to prevent damage to the gate oxide layer. The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode. We etch the gate stack and the endpoint detect layer using a multi-step etch comprising at least 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped. In an endpoint detect layer etch step, the gate stack layer and the endpoint detect layer are etched using a second etch chemistry. The endpoint etch step is stopped when an endpoint detect signal changes upon reaching the gate dielectric layer. The second etch chemistry has a higher selectivity from the gate dielectric layer to the gate stack layer and endpoint detect layer than the first etch chemistry. In an overetch step, using a third etch chemistry with a higher selectivity than the second etch chemistry, we etch the endpoint detect layer without damaging the gate dielectric layer.
摘要翻译：一种制造具有端点检测层和多步骤蚀刻工艺以防止损坏栅极电介质层的栅极堆叠的方法。特殊端点检测层发射端点信号，允许将蚀刻化学物质改变为更具选择性的多晶硅与氧化物比例，以防止对栅极氧化物层的损坏。本发明通过在衬底上形成栅极电介质层开始。然后，我们在栅极电介质层上形成端点检测层。在底部硅层上形成栅极叠层。然后在栅极堆叠上形成掩模。掩模限定栅电极。我们使用包括至少3个步骤的多步骤蚀刻来蚀刻栅极堆叠和端点检测层。在主蚀刻步骤中，使用第一蚀刻化学品蚀刻栅极堆叠和端点检测层。在通过蚀刻栅极堆叠产生的端点检测信号时，停止第一蚀刻步骤。在端点检测层蚀刻步骤中，使用第二蚀刻化学法蚀刻栅极堆叠层和端点检测层。当端点检测信号在到达栅极电介质层时改变时，停止端点蚀刻步骤。第二蚀刻化学物质具有比第一蚀刻化学物质更高的从栅极介电层到栅极堆叠层和端点检测层的选择性。在过蚀刻步骤中，使用比第二蚀刻化学品更高选择性的第三蚀刻化学品，我们蚀刻端点检测层而不损坏栅极电介质层。

4. 发明授权

US06709918B1 Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology 有权
标题翻译：用于铜后端（BEOL）技术的金属绝缘体金属（MIM）电容器和金属电阻器的制造方法
公开(公告)号：US06709918B1
公开(公告)日：2004-03-23
申请号：US10307674
申请日：2002-12-02
申请人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
发明人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L28/20 , H01L23/5223 , H01L23/5228 , H01L28/40 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si3N4 or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.
摘要翻译：实现了一种在金铜绝缘体金属（MIM）电容器和金属电阻器Cu铜镶嵌后端工艺中的制造方法。该方法使用双镶嵌工艺形成Cu电容器底部金属板。沉积Si 3 N 4或SiC以在Cu底板上形成电容器电介质层。具有上蚀刻停止层的金属层被沉积并图案化以形成电容器顶板和金属电阻器。图案化终止在电容器电介质层中以防止Cu颗粒污染。沉积绝缘层，并且使用上蚀刻停止层将电容器顶板和金属电阻器的通孔蚀刻以防止过蚀刻和损坏。该方法提供了仅使用一种附加光致抗蚀剂掩模的MIM电容器，同时提高了工艺产量。

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