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1. 发明授权

US06281093B1 Method to reduce trench cone formation in the fabrication of shallow trench isolations 失效
标题翻译：在浅沟槽隔离制造中减少沟槽形成的方法
公开(公告)号：US06281093B1
公开(公告)日：2001-08-28
申请号：US09619016
申请日：2000-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Qinghua Zhong , Zheng Zou , Henry Gerung
发明人： Yelehanka Ramachandramurthy Pradeep , Qinghua Zhong , Zheng Zou , Henry Gerung
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/76224
摘要： A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
摘要翻译：已经实现了制造浅沟槽隔离的新方法。在半导体衬底上形成二氧化硅层。沉积氮化硅层覆盖二氧化硅层。图案化氮化硅层以暴露其中规划浅沟槽隔离的半导体衬底。将离子注入到暴露的半导体衬底中。植入损伤覆盖半导体衬底的任何被动表面材料。暴露的半导体衬底被蚀刻以形成沟槽。在蚀刻期间，损坏的被动表面材料被去除，从而防止形成沟槽。沉积沟槽填充层以填充沟槽。在集成电路器件的制造中，沟槽填充层被抛光以完成浅沟槽隔离。

2. 发明授权

US08298949B2 Profile and CD uniformity control by plasma oxidation treatment 有权
标题翻译：通过等离子体氧化处理的轮廓和CD均匀性控制
公开(公告)号：US08298949B2
公开(公告)日：2012-10-30
申请号：US12350060
申请日：2009-01-07
申请人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
发明人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
IPC分类号： H01L21/311
CPC分类号： H01L21/32105 , H01L21/02323 , H01L21/02326 , H01L21/31116 , H01L29/6656
摘要： A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.
摘要翻译：提供了一种从非氧化硅形成间隔物的方法，在衬底上方具有水平表面和侧壁表面的含硅隔离层。提供等离子体氧化处理以在间隔层上形成氧化硅涂层，其中氧化硅涂层在间隔层的侧壁表面上的水平表面和侧壁涂层上提供水平涂层。提供了选择性地蚀刻间隔层和氧化硅涂层的水平表面相对于间隔层的侧壁表面和氧化硅涂层的侧壁涂层的各向异性主蚀刻。间隔层被蚀刻，其中氧化硅涂层的侧壁涂层保护间隔层的侧壁表面。

3. 发明授权

US6001706A Method for making improved shallow trench isolation for semiconductor integrated circuits 失效
标题翻译：用于半导体集成电路改进浅沟槽隔离的方法
公开(公告)号：US6001706A
公开(公告)日：1999-12-14
申请号：US986670
申请日：1997-12-08
申请人： Poh Suan Tan , Lap Chan , Qinghua Zhong , Qian Gang
发明人： Poh Suan Tan , Lap Chan , Qinghua Zhong , Qian Gang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas. This eliminates the wrap-around corner effect which in the prior art resulted in enhanced corner conduction and increased sub-threshold leakage currents at substrate back bias. This improved method also provides greater processing latitude during the chemical mechanical polish step.
摘要翻译：实现了一种用于制造具有自对准并在器件区域的边缘上延伸的凸起部分的场氧化物区域（浅沟槽隔离）的方法。这导致FET具有改进的亚阈值特性和较低的亚阈值漏电流。该方法包括在硅衬底上形成衬垫氧化物并沉积掺杂多晶硅层和硬掩模层。浅沟槽通过硬掩模，掺杂多晶硅层并部分地蚀刻到硅衬底中。使用热氧化在沟槽中形成衬垫氧化物，并以更高的氧化速率氧化掺杂多晶硅层的侧壁，以在器件区域的边缘上形成氧化物。间隙填充氧化物沉积在沟槽和化学机械抛光（CMP）中回到多晶硅层。选择性地去除器件区域上的剩余多晶硅层以提供具有形成在器件区域的边缘上的凸起部分的场氧化物。这消除了环绕拐角效应，其在现有技术中导致增强的拐角传导和在衬底背偏压下增加的次阈值泄漏电流。这种改进的方法还在化学机械抛光步骤期间提供更大的加工纬度。

4. 发明申请

US20100173496A1 PROFILE AND CD UNIFORMITY CONTROL BY PLASMA OXIDATION TREATMENT 有权
标题翻译：简介和CD等离子体氧化处理的均匀性控制
公开(公告)号：US20100173496A1
公开(公告)日：2010-07-08
申请号：US12350060
申请日：2009-01-07
申请人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
发明人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
IPC分类号： H01L21/4757
CPC分类号： H01L21/32105 , H01L21/02323 , H01L21/02326 , H01L21/31116 , H01L29/6656
摘要： A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.
摘要翻译：提供了一种从非氧化硅形成间隔物的方法，在衬底上方具有水平表面和侧壁表面的含硅隔离层。提供等离子体氧化处理以在间隔层上形成氧化硅涂层，其中氧化硅涂层在间隔层的侧壁表面上的水平表面和侧壁涂层上提供水平涂层。提供了选择性地蚀刻间隔层和氧化硅涂层的水平表面相对于间隔层的侧壁表面和氧化硅涂层的侧壁涂层的各向异性主蚀刻。间隔层被蚀刻，其中氧化硅涂层的侧壁涂层保护间隔层的侧壁表面。

5. 发明申请

US20080087639A1 LINE END SHORTENING REDUCTION DURING ETCH 有权
标题翻译：在ETCH期间的线端缩短
公开(公告)号：US20080087639A1
公开(公告)日：2008-04-17
申请号：US11621902
申请日：2007-01-10
申请人： Yoko Adams , Gowri Kota , Frank Lin , Qinghua Zhong
发明人： Yoko Adams , Gowri Kota , Frank Lin , Qinghua Zhong
IPC分类号： C03C25/68
CPC分类号： H01L21/31144 , H01L21/0212 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/0273 , H01L21/31058 , H01L21/312 , H01L21/3127 , H01L21/32139
摘要： A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.
摘要翻译：提供了一种用于蚀刻蚀刻层中的特征的方法。提供了图案化的光致抗蚀剂掩模在蚀刻层之上，光刻胶掩模具有至少一个光致抗蚀剂线，其具有在线端终止的一对侧壁。聚合物层放置在至少一个光致抗蚀剂线之上，其中在光致抗蚀剂线的线端处的聚合物层的厚度大于光致抗蚀剂线的侧壁上的聚合物层的厚度。通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中，其中线端缩短（LES）比小于或等于1。

6. 发明授权

US6124927A Method to protect chamber wall from etching by endpoint plasma clean 失效
标题翻译：通过端点血浆清洁来保护腔室壁免受蚀刻的方法
公开(公告)号：US6124927A
公开(公告)日：2000-09-26
申请号：US314589
申请日：1999-05-19
申请人： Qinghua Zhong , Zou Zheng , Yelehanka Ramachandra Murthy Pradeep , Zhou Mei Sheng
发明人： Qinghua Zhong , Zou Zheng , Yelehanka Ramachandra Murthy Pradeep , Zhou Mei Sheng
IPC分类号： G01J3/443 , H01J37/32 , G01J3/30 , C23C16/00
CPC分类号： H01J37/32862 , G01J3/443 , H01J37/32935 , H01J37/32963
摘要： A new method of controlling the level of cleaning of the etch chamber by measuring the light emission caused by particles within the plasma of the etch chamber. The etch chamber clean process is invoked as soon as the level of contaminants within the etch chamber is observed as being too high. This measuring of the contaminants within the etch chamber is performed by measuring the particle light emission. The etch chamber cleaning process is considered complete when the light intensity created by existing particles in the chamber drops by a certain percentage.
摘要翻译：通过测量由蚀刻室的等离子体内的颗粒引起的光发射来控制蚀刻室的清洁水平的新方法。一旦观察到蚀刻室内的污染物浓度太高，就会调用蚀刻室清洁过程。通过测量颗粒光发射来测量蚀刻室内的污染物。当室内现有颗粒产生的光强度下降一定百分比时，蚀刻室清洁过程被认为是完整的。

7. 发明授权

US08668805B2 Line end shortening reduction during etch 有权
标题翻译：刻蚀期间线端缩短缩短
公开(公告)号：US08668805B2
公开(公告)日：2014-03-11
申请号：US12165539
申请日：2008-06-30
申请人： Gowri Kota , Frank Y. Lin , Qinghua Zhong
发明人： Gowri Kota , Frank Y. Lin , Qinghua Zhong
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/31058 , H01L21/32139
摘要： A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.
摘要翻译：半导体器件可以通过以下方法形成：包括在蚀刻层上提供经图案化的光致抗蚀剂掩模，光致抗蚀剂掩模具有至少一个光致抗蚀剂线，其具有终止于线端的一对侧壁，将涂层置于至少一个光致抗蚀剂线包括至少一个循环，其中每个循环包括：a）在所述光致抗蚀剂线上沉积聚合物层，其中所述一端的聚合物的量大于所述侧壁上的聚合物的量，以及b）使所述聚合物层硬化，并通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中，其中线端缩短（LES）小于或等于1。

8. 发明授权

US07491343B2 Line end shortening reduction during etch 有权
标题翻译：刻蚀期间线端缩短缩短
公开(公告)号：US07491343B2
公开(公告)日：2009-02-17
申请号：US11621902
申请日：2007-01-10
申请人： Yoko Yamaguchi Adams , Gowri Kota , Frank Y. Lin , Qinghua Zhong
发明人： Yoko Yamaguchi Adams , Gowri Kota , Frank Y. Lin , Qinghua Zhong
IPC分类号： B44C1/22
CPC分类号： H01L21/31144 , H01L21/0212 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/0273 , H01L21/31058 , H01L21/312 , H01L21/3127 , H01L21/32139
摘要： A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.
摘要翻译：提供了一种用于蚀刻蚀刻层中的特征的方法。提供了图案化的光致抗蚀剂掩模在蚀刻层之上，光刻胶掩模具有至少一个光致抗蚀剂线，其具有在线端终止的一对侧壁。聚合物层放置在至少一个光致抗蚀剂线之上，其中在光致抗蚀剂线的线端处的聚合物层的厚度大于光致抗蚀剂线的侧壁上的聚合物层的厚度。通过光致抗蚀剂掩模将特征蚀刻到蚀刻层中，其中线端缩短（LES）比小于或等于1。

9. 外观设计

USD967308S1 Resistance band 有权
公开(公告)号：USD967308S1
公开(公告)日：2022-10-18
申请号：US29804240
申请日：2021-08-19
申请人： Qinghua Zhong
设计人： Qinghua Zhong

10. 外观设计

USD863470S1 Anti-skid resistance band 有权
公开(公告)号：USD863470S1
公开(公告)日：2019-10-15
申请号：US29692159
申请日：2019-05-23
申请人： Qinghua Zhong
设计人： Qinghua Zhong
摘要： FIG. 1 is a perspective view of an anti-skid resistance band showing my design;
FIG. 2 is a front view thereof;
FIG. 3 is a back view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof; and,
FIG. 8 is an enlarged view of the selected portion in FIG. 1.

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