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1. 发明授权

US4954866A Semiconductor integrated circuit memory 失效
标题翻译：半导体集成电路存储器
公开(公告)号：US4954866A
公开(公告)日：1990-09-04
申请号：US247250
申请日：1988-09-21
申请人： Hirotoshi Tanaka , Hiroki Yamashita , Noboru Masuda , Junji Shigeta , Yasunari Umemoto , Osamu Kagaya
发明人： Hirotoshi Tanaka , Hiroki Yamashita , Noboru Masuda , Junji Shigeta , Yasunari Umemoto , Osamu Kagaya
IPC分类号： H01L27/06 , H01L27/105 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0605 , H01L27/1116 , H01L27/105
摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.
摘要翻译：公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下由载流子浓度低的P型层构成。形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加外围电路部分保持高速运行的内存。

2. 发明授权

US5027167A Semiconductor intergrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5027167A
公开(公告)日：1991-06-25
申请号：US175705
申请日：1988-03-31
申请人： Osamu Kagaya , Yasunari Umemoto , Junji Shigeta
发明人： Osamu Kagaya , Yasunari Umemoto , Junji Shigeta
IPC分类号： H01L21/761 , H01L21/338 , H01L21/76 , H01L21/765 , H01L27/10 , H01L29/812
CPC分类号： H01L21/765 , H01L21/7605
摘要： The semiconductor integrated circuit of the present invention includes an electrode to which potential is supplied to apply an electric field to an isolation layer between similar semiconductor layers having ohmic electrodes and implanted into a compound semiconductor substrate. By this construction this invention reduces the development of temporary conduction in the isolation layer due to disturbance of potential barrier by .alpha. particles, and can improve pronouncedly the tolerance to .alpha. particle induced soft errors.
摘要翻译：本发明的半导体集成电路包括提供电位的电极，用于向具有欧姆电极的类似半导体层之间的隔离层施加电场并注入到化合物半导体衬底中。通过这种结构，本发明减少了由于α粒子对势垒的干扰而导致的隔离层临时传导的发展，并且可以显着改善对α粒子诱导的软错误的耐受性。

3. 发明授权

US5132752A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5132752A
公开(公告)日：1992-07-21
申请号：US658463
申请日：1991-02-22
申请人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
发明人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
IPC分类号： H01L29/10 , H01L29/812
CPC分类号： H01L29/1075 , H01L29/812 , Y10S257/903
摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
摘要翻译：形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。第二半导体层被掺杂以使其完全耗尽。因此，与衬底相邻的第二半导体层的一部分将保持导电。具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

4. 发明授权

US5068605A Semiconductor integrated circuit device and method of testing the same 失效
标题翻译：半导体集成电路器件及其测试方法
公开(公告)号：US5068605A
公开(公告)日：1991-11-26
申请号：US404355
申请日：1989-09-07
申请人： Moritoshi Yasunaga , Noboru Masuda , Hideo Todokoro , Yasunari Umemoto , Hirotoshi Tanaka , Hiroyuki Itoh
发明人： Moritoshi Yasunaga , Noboru Masuda , Hideo Todokoro , Yasunari Umemoto , Hirotoshi Tanaka , Hiroyuki Itoh
IPC分类号： G01R31/28 , G01R31/30 , G01R31/302 , G01R31/305 , G01R31/3185 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/305 , G01R31/30 , G01R31/318516
摘要： A semiconductor integrated circuit device includes: input terminals; output terminals; a group of gates which receives an input signal applied to the input terminals and outputs an output signal from the output terminals, the output signal corresponding to the state of the input signal; and an arrangement for forcibly setting the output of each gate constituting the group either at a "1" level or at a "0" level irrespective of the state of the input signal and the state of an input signal to each gate. The arrangement for forcibly setting the output is an arrangement for changing the potential of a semiconductor substrate in which each gate is formed. This arrangement for changing potential includes an impurity doped region formed in the semiconductor substrate, the impurity doped region surrounding at least a transistor constituting each gate so as to apply a potential to the transistor, and a terminal for applying the potential to the impurity doped region. The semiconductor integrated circuit device according to another aspect includes an observation pad formed on a portion of at least one of the output and input areas of each gate, the observation pad being exposed without being covered with an insulator layer and the potential of the observation pad being observed as a difference of shading by using an electron or ion beam tester. A fault of each gate can be detected in accordance with a shading image of the observation pads.
摘要翻译：半导体集成电路装置包括：输入端子; 输出端子; 一组门，其接收施加到输入端的输入信号，并输出来自输出端的输出信号，输出信号对应于输入信号的状态; 以及用于强制地将构成组的每个门的输出强制设置为“1”电平或“0”电平的装置，而与输入信号的状态和每个门的输入信号的状态无关。用于强制设置输出的布置是用于改变其中形成每个栅极的半导体衬底的电位的布置。这种用于变化电位的布置包括形成在半导体衬底中的杂质掺杂区域，至少构成每个栅极的晶体管的杂质掺杂区域，以便向晶体管施加电位，以及将电位施加到杂质掺杂区域。根据另一方面的半导体集成电路器件包括形成在每个栅极的输出和输入区域中的至少一个的一部分上的观察垫，观察垫被暴露而不被绝缘体层覆盖，并且观察垫的电位通过使用电子或离子束测试仪被观察为阴影的差异。可以根据观察垫的阴影图像来检测每个门的故障。

5. 发明授权

US06636118B1 High-frequency power amplification module and radio communication device 失效
标题翻译：高频功率放大模块和无线通信设备
公开(公告)号：US06636118B1
公开(公告)日：2003-10-21
申请号：US09914678
申请日：2001-11-14
申请人： Cyushiro Kusano , Eiichi Hase , Hideyuki Ono , Osamu Kagaya , Yasunari Umemoto , Takahiro Fujita , Kiichi Yamashita
发明人： Cyushiro Kusano , Eiichi Hase , Hideyuki Ono , Osamu Kagaya , Yasunari Umemoto , Takahiro Fujita , Kiichi Yamashita
IPC分类号： H03F304
CPC分类号： H01L27/0255 , H03F1/52 , H03F3/195 , H03F2200/444 , H03F2203/21178
摘要： In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series is connected between the collector and emitter of each HBT. The p-side is connected to the collector side, and the n-side is connected to the emitter side. A protection circuit in which pn junction diodes of the number equal to or smaller than that of the pn junction diodes are connected in series is connected between the base and the emitter. The p-side is connected to the base side, and the n-side is connected to the emitter side. With the configuration, in the case where an overvoltage is applied across the collector and emitter due to a fluctuation in load on the antenna side, the collector terminal is clamped by an ON-state voltage of the protection circuits, so that the HBT can be prevented from being destroyed. Since the similar protection circuit is assembled between the base and emitter, even when the operator touches the module at the time of manufacturing the high frequency power amplifier module, the HBT can be prevented from being destroyed by the clamping effect of the protection circuit between the base and emitter and the protection circuit between the collector and emitter. Thus, an improved manufacturing yield of the high frequency power amplifier module and a wireless communication apparatus can be achieved, and destruction caused by fluctuation in load impedance of the wireless communication apparatus can be prevented.
摘要翻译：在其中级联多个异质结双极型晶体管（npn型HBT）的多级结构的高频功率放大器模块中，将多个pn结二极管串联连接的保护电路连接在每个HBT的集电极和发射极。 p侧连接到集电极侧，并且n侧连接到发射极侧。其中pn结二极管的数量等于或小于pn结二极管串联的保护电路连接在基极和发射极之间。 p侧连接到基极侧，并且n侧连接到发射极侧。通过该结构，由于天线侧的负载的波动，在集电极和发射极两端施加过电压的情况下，集电端子被保护电路的导通状态电压钳位，HBT可以防止被摧毁。由于类似的保护电路组装在基极和发射极之间，即使在制造高频功率放大器模块时操作者接触模块时，也可以防止HBT被保护电路的钳位效应所破坏基极和发射极以及集电极和发射极之间的保护电路。因此，可以实现高频功率放大器模块和无线通信装置的制造成品率的提高，并且可以防止由无线通信装置的负载阻抗的波动引起的破坏。

6. 发明授权

US5124770A Field effect transistor with alpha particle protection 失效
标题翻译：具有α粒子保护的场效应晶体管
公开(公告)号：US5124770A
公开(公告)日：1992-06-23
申请号：US512501
申请日：1990-04-20
申请人： Yasunari Umemoto , Kiichi Ueyanagi , Junji Shigeta , Norikazu Hashimoto
发明人： Yasunari Umemoto , Kiichi Ueyanagi , Junji Shigeta , Norikazu Hashimoto
IPC分类号： H01L29/812 , H01L21/338 , H01L29/10
CPC分类号： H01L29/1075 , Y10S257/903
摘要： An FET structure with improved .alpha.-particle immunity or soft error immunity particularly provided in a semi-insulating substrate. This structure includes some layer which can prevent both electrons and holes generated in a substrate by the incidence of .alpha.-particles from being injected into the FET.
摘要翻译：特别是在半绝缘衬底中提供了具有改进的α-粒子抗扰度或软错误抗扰性的FET结构。该结构包括一些层，其可以通过注入到FET中的α粒子的入射来防止在衬底中产生的电子和空穴。

7. 发明申请

US20070164316A1 Heterojunction bipolar transistor and method for manufacturing the same, and power amplifier using the same 有权
公开(公告)号：US20070164316A1
公开(公告)日：2007-07-19
申请号：US11723769
申请日：2007-03-22
申请人： Isao Ohbu , Chushiro Kusano , Yasunari Umemoto , Atsushi Kurokawa
发明人： Isao Ohbu , Chushiro Kusano , Yasunari Umemoto , Atsushi Kurokawa
IPC分类号： H01L31/00
CPC分类号： H01L29/7304 , H01L27/0605 , H01L29/7371 , H03F2200/444 , H03F2203/21178
摘要： A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

8. 发明申请

US20060138460A1 Semiconductor device and radio communication device 有权
标题翻译：半导体器件和无线电通信设备
公开(公告)号：US20060138460A1
公开(公告)日：2006-06-29
申请号：US11319084
申请日：2005-12-28
申请人： Satoshi Sasaki , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
发明人： Satoshi Sasaki , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
IPC分类号： H01L31/109
CPC分类号： H01L29/7304 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/042 , H01L27/0605 , H01L27/067 , H01L28/40 , H01L29/0808 , H01L29/7371 , H01L2223/6627 , H01L2223/6644 , H01L2224/05553 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01041 , H01L2924/01042 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/19032 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099
摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.
摘要翻译：提供了允许半导体器件的热阻降低和小型化的技术。半导体器件具有多个单位晶体管Q，具有第一数量（7）的单位晶体管Q的晶体管形成区域3a，3b和3e，以及分别具有第二（4个）晶体管Q.晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，第一个数量大于第二个数量。

9. 发明授权

US07045877B2 Semiconductor protection device 失效
标题翻译：半导体保护装置
公开(公告)号：US07045877B2
公开(公告)日：2006-05-16
申请号：US10420740
申请日：2003-04-23
申请人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
发明人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
IPC分类号： H01L31/072
CPC分类号： H01L27/0825 , H01L27/0259 , H01L29/7371 , H01L2224/48091 , H01L2224/73265 , H03K17/08146 , H03K17/615 , H01L2924/00014
摘要： The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.
摘要翻译：本发明旨在提高对半导体器件的破坏性。具有连接在高输出的放大电路的输出（集电极和发射极）之间的达林顿的多个双极晶体管的保护电路与放大电路并联电连接。放大电路具有彼此并联连接的多个单元HBT（异质结双极晶体管）。保护电路具有包括具有多个双极型晶体管Q 1至Q 5的第一组保护电路和具有多个双极晶体管的第二组保护电路的两级配置。

10. 发明授权

US08860093B2 Semiconductor device and radio communication device 有权
标题翻译：半导体器件和无线电通信设备
公开(公告)号：US08860093B2
公开(公告)日：2014-10-14
申请号：US13538121
申请日：2012-06-29
申请人： Satoshi Sasaki , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
发明人： Satoshi Sasaki , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
IPC分类号： H01L27/102 , H01L29/737 , H03F3/195 , H01L23/66 , H01L27/06 , H01L23/00
CPC分类号： H01L29/7304 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/042 , H01L27/0605 , H01L27/067 , H01L28/40 , H01L29/0808 , H01L29/7371 , H01L2223/6627 , H01L2223/6644 , H01L2224/05553 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01041 , H01L2924/01042 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/19032 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099
摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
摘要翻译：提供了允许降低无线电通信装置中使用的半导体装置的热阻的技术及其小型化。例如，半导体器件可以包括多个单位晶体管Q，具有单位晶体管Q的第一数量（例如7个）的晶体管形成区域3a，3b和3e以及每个具有单位晶体管Q的晶体管形成区域3c和3d 晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，第一数量大于第二数量。

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