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    • 1. 发明授权
    • Semiconductor integrated circuit memory
    • 半导体集成电路存储器
    • US4954866A
    • 1990-09-04
    • US247250
    • 1988-09-21
    • Hirotoshi TanakaHiroki YamashitaNoboru MasudaJunji ShigetaYasunari UmemotoOsamu Kagaya
    • Hirotoshi TanakaHiroki YamashitaNoboru MasudaJunji ShigetaYasunari UmemotoOsamu Kagaya
    • H01L27/06H01L27/105H01L27/11
    • H01L27/1104H01L27/0605H01L27/1116H01L27/105
    • A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.
    • 公开了一种半导体集成电路存储器,其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层,例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式,并且被划分为至少第一和第二区域。 例如,形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成,并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫,即使当存储单元的尺寸精细时。 此外,形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力,并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。
    • 6. 发明授权
    • Optical integrated device, semiconductor laser module and optical transmitter
    • 光学集成器件,半导体激光器模块和光发射机
    • US06678432B2
    • 2004-01-13
    • US09785451
    • 2001-02-20
    • Junji ShigetaKimio TatsunoMasataka Shirai
    • Junji ShigetaKimio TatsunoMasataka Shirai
    • G02B613
    • H01S5/02216H01S5/02415H01S5/026H01S5/0264H01S5/0683H01S5/4031
    • To resolve a problem in which in an optical output and wavelength monitor integrated type semiconductor laser module monolithically integrated in parallel with a plurality of semiconductor lasers, since light emitting positions of the respective semiconductor lasers differ, an allowable range of an optical incident position of the monitor is exceeded, the optical incident position of the monitor is confined in the allowable range by integrating backward optical waveguides for guiding backward beam of the respective semiconductor lasers to a narrow range at a backward end of a semiconductor chip along with the semiconductor lasers, whereby there can be easily realized a semiconductor laser module with a built-in optical monitor even in the case of the chip integrated with the plurality of semiconductor lasers and can be realized an inexpensive optical module having high function.
    • 为了解决在与多个半导体激光器并联地单片集成的光输出和波长监视器集成型半导体激光器模块中的问题,由于各个半导体激光器的发光位置不同,所以光入射位置的允许范围 监视器被超过,通过将反射光波导集成在半导体激光器的半导体芯片的后端,将各个半导体激光器的反向光束集成到窄范围内,将监视器的光学入射位置限制在允许范围内,由此 即使在与多个半导体激光器集成的芯片的情况下,也可以容易地实现具有内置光学监视器的半导体激光器模块,并且可以实现具有高功能的便宜的光学模块。
    • 9. 发明授权
    • Optical transmission apparatus and bidirectional optical space transmission system using the same
    • 光传输装置和双向光空间传输系统采用相同的方式
    • US06616352B1
    • 2003-09-09
    • US09586883
    • 2000-06-05
    • Junji ShigetaToshihiko MyojoYasuhiro TakahashiKazuo Moritomo
    • Junji ShigetaToshihiko MyojoYasuhiro TakahashiKazuo Moritomo
    • H04B1000
    • H04B10/1125
    • A bidirectional optical space transmission system is made up of a pair of optical transmission apparatus. Each optical transmission apparatus comprises a signal generating circuit for generating a pilot signal, a multiplexing section for multiplexing the pilot signal and a main signal to be transmitted, an electrooptic converter section for emitting an optical signal on the basis of the signal produced by the multiplexing process, a light receiving element for receiving an optical signal transmitted from the partner optical transmission apparatus and detecting a pilot signal contained therein, and a demodulation circuit for demodulating the pilot signal detected by the light receiving element. Pilot signals multiplexed with main signals to be transmitted through the bidirectional optical transmission system are subjected to spreading modulation and demodulated for spreading by the demodulation circuit.
    • 双向光学空间传输系统由一对光传输装置组成。 每个光传输装置包括用于产生导频信号的信号发生电路,用于复用导频信号的复用部分和要传输的主信号,基于由多路复用产生的信号发射光信号的电光转换器部分 处理光接收元件,用于接收从伙伴光传输装置发送的光信号并检测其中包含的导频信号;以及解调电路,用于解调由光接收元件检测的导频信号。 对通过双向光传输系统发送的主信号进行多路复用的导频信号经过扩展调制,并由解调电路进行解调以进行扩频。
    • 10. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07619911B2
    • 2009-11-17
    • US10579911
    • 2003-11-21
    • Satoru HanzawaJunji ShigetaShinichiro KimuraTakeshi SakataRiichiro TakemuraKazuhiko Kajigaya
    • Satoru HanzawaJunji ShigetaShinichiro KimuraTakeshi SakataRiichiro TakemuraKazuhiko Kajigaya
    • G11C15/00
    • G11C15/04G11C15/043
    • In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
    • 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中,将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极,构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外,匹配检测器MDr布置在预充电到低电压的匹配线LMLr上,以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作,可以在低功率和高速度下执行比较操作,同时在匹配线对中避免搜索线噪声的影响。 因此,可以实现允许高速搜索操作的低功率内容可寻址存储器。