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1. 发明申请

US20100173497A1 Method of fabricating semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100173497A1
公开(公告)日：2010-07-08
申请号：US12655837
申请日：2010-01-06
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
IPC分类号： H01L21/306
CPC分类号： H01L21/32139
摘要： A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.
摘要翻译：制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

2. 发明授权

US08518723B2 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US08518723B2
公开(公告)日：2013-08-27
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层来形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

3. 发明申请

US20100136790A1 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100136790A1
公开(公告)日：2010-06-03
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

4. 发明授权

US07595253B2 Method of forming the semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07595253B2
公开(公告)日：2009-09-29
申请号：US11797827
申请日：2007-05-08
申请人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

5. 发明申请

US20070262393A1 Semiconductor devices and methods of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070262393A1
公开(公告)日：2007-11-15
申请号：US11797827
申请日：2007-05-08
申请人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L29/76 , H01L21/76 , H01L21/461 , H01L29/94 , H01L21/302 , H01L31/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

6. 发明申请

US20070258075A1 Apparatus for processing a semiconductor wafer and method of forming the same 审中-公开
标题翻译：用于处理半导体晶片的设备及其形成方法
公开(公告)号：US20070258075A1
公开(公告)日：2007-11-08
申请号：US11790175
申请日：2007-04-24
申请人： Ki-Chul Kim , Hong-Jae Shin , Nae-In Lee
发明人： Ki-Chul Kim , Hong-Jae Shin , Nae-In Lee
IPC分类号： G03B27/52
CPC分类号： H01L21/68721
摘要： A semiconductor wafer processing apparatus may include a chuck and/or a focus ring. The chuck may be configured to hold a wafer. The focus ring may be disposed surrounding a rim of the chuck. The focus ring may include a first section formed of a first material and a second section formed of a second material. The first material and the second material may have different conductivities. A method of forming a semiconductor wafer processing apparatus may include forming a first section of a focus ring from a first material, forming a second section of the focus ring from a second material having a different conductivity than the first material, combining the first and second sections to form a focus ring, and/or arranging the focus ring so as to surround a chuck.
摘要翻译：半导体晶片处理装置可以包括卡盘和/或聚焦环。卡盘可以被配置成保持晶片。聚焦环可以围绕卡盘的边缘设置。聚焦环可以包括由第一材料形成的第一部分和由第二材料形成的第二部分。第一材料和第二材料可以具有不同的电导率。形成半导体晶片处理装置的方法可以包括从第一材料形成聚焦环的第一部分，从具有不同于第一材料的导电率的第二材料形成聚焦环的第二部分，将第一和第二部分形成聚焦环，和/或配置聚焦环以围绕卡盘。

7. 发明申请

US20060289999A1 Selective copper alloy interconnections in semiconductor devices and methods of forming the same 审中-公开
标题翻译：半导体器件中的选择性铜合金互连及其形成方法
公开(公告)号：US20060289999A1
公开(公告)日：2006-12-28
申请号：US11389868
申请日：2006-03-27
申请人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
发明人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76846 , H01L21/76847 , H01L21/76864 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.
摘要翻译：提供半导体器件中的选择性铜合金互连。互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。第一个互连具有第一个纯铜图案。此外，在电介质中形成具有大于第一互连的宽度的第二互连。第二互连具有铜合金图案。铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。还提供了形成选择性铜合金图案的方法。

8. 发明授权

US07307014B2 Method of forming a via contact structure using a dual damascene process 有权
标题翻译：使用双镶嵌工艺形成通孔接触结构的方法
公开(公告)号：US07307014B2
公开(公告)日：2007-12-11
申请号：US11099534
申请日：2005-04-06
申请人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
发明人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.
摘要翻译：公开了一种使用双镶嵌工艺形成通孔接触结构的方法。根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

9. 发明申请

US20060003574A1 Method of forming a via contact structure using a dual damascene process 有权
标题翻译：使用双镶嵌工艺形成通孔接触结构的方法
公开(公告)号：US20060003574A1
公开(公告)日：2006-01-05
申请号：US11099534
申请日：2005-04-06
申请人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
发明人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.
摘要翻译：公开了一种使用双镶嵌工艺形成通孔接触结构的方法。根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

10. 发明授权

US08357576B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08357576B2
公开(公告)日：2013-01-22
申请号：US13007096
申请日：2011-01-14
申请人： Chong-Kwang Chang , Sung-Hon Chi , Hong-Jae Shin , Yong-Jin Chung , Young-Mook Oh , Ju-Beom Yi
发明人： Chong-Kwang Chang , Sung-Hon Chi , Hong-Jae Shin , Yong-Jin Chung , Young-Mook Oh , Ju-Beom Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.
摘要翻译：一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

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