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1. 发明申请

US20060003574A1 Method of forming a via contact structure using a dual damascene process 有权
标题翻译：使用双镶嵌工艺形成通孔接触结构的方法
公开(公告)号：US20060003574A1
公开(公告)日：2006-01-05
申请号：US11099534
申请日：2005-04-06
申请人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
发明人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.
摘要翻译：公开了一种使用双镶嵌工艺形成通孔接触结构的方法。根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

2. 发明授权

US07307014B2 Method of forming a via contact structure using a dual damascene process 有权
标题翻译：使用双镶嵌工艺形成通孔接触结构的方法
公开(公告)号：US07307014B2
公开(公告)日：2007-12-11
申请号：US11099534
申请日：2005-04-06
申请人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
发明人： Jae-Hak Kim , Kyoung-Woo Lee , Hong-Jae Shin , Young-Joon Moon , Seo-Woo Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.
摘要翻译：公开了一种使用双镶嵌工艺形成通孔接触结构的方法。根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

3. 发明授权

US07064059B2 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer 有权
标题翻译：使用牺牲金属氧化物层形成双镶嵌金属互连的方法
公开(公告)号：US07064059B2
公开(公告)日：2006-06-20
申请号：US10939930
申请日：2004-09-13
申请人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
发明人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
IPC分类号： H01L21/4763 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76808 , H01L21/31144
摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.
摘要翻译：提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。该方法包括制备半导体衬底。在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

4. 发明申请

US20050124149A1 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer 有权
标题翻译：使用牺牲金属氧化物层形成双镶嵌金属互连的方法
公开(公告)号：US20050124149A1
公开(公告)日：2005-06-09
申请号：US10939930
申请日：2004-09-13
申请人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
发明人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808 , H01L21/31144
摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.
摘要翻译：提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。该方法包括制备半导体衬底。在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

5. 发明申请

US20060183280A1 Metal-insulator-metal capacitors and methods of forming the same 审中-公开
标题翻译：金属绝缘体金属电容器及其形成方法
公开(公告)号：US20060183280A1
公开(公告)日：2006-08-17
申请号：US11352660
申请日：2006-02-13
申请人： Sang-Jin Lee , Young-Joon Moon , Seung-Koo Lee , Kyung-Tae Lee
发明人： Sang-Jin Lee , Young-Joon Moon , Seung-Koo Lee , Kyung-Tae Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/76816 , H01L21/76807 , H01L28/60
摘要： There are provided metal-insulator-metal (MIM) capacitors and methods of forming the same. The capacitors and the formation methods thereof provide a way of simplifying semiconductor fabrication processes, using component elements of the capacitor and insulating layers around the capacitor. To this end, lower and upper electrodes are sequentially stacked on a semiconductor substrate. A dielectric layer pattern is interposed between the upper and lower electrodes. An etch stop layer pattern and an etch buffer layer are disposed on the upper electrode and under the lower electrode, respectively. The upper and lower electrodes are disposed to expose the dielectric layer pattern and the etch buffer layer.
摘要翻译：提供金属 - 绝缘体 - 金属（MIM）电容器及其形成方法。电容器及其形成方法提供了使用电容器的元件和电容器周围的绝缘层来简化半导体制造工艺的方法。为此，下电极和上电极依次堆叠在半导体衬底上。电介质层图案插入在上电极和下电极之间。蚀刻停止层图案和蚀刻缓冲层分别设置在上电极和下电极下。上电极和下电极被设置为暴露电介质层图案和蚀刻缓冲层。

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