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1. 发明授权

US06680239B1 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant 失效
标题翻译：有效的隔离与高纵横比浅沟槽隔离和氧或野外植入
公开(公告)号：US06680239B1
公开(公告)日：2004-01-20
申请号：US09624025
申请日：2000-07-24
申请人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
发明人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.
摘要翻译：给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。然后将氧或场隔离离子注入到沟槽的底部。然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

2. 发明授权

US06319767B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique 有权
标题翻译：用于通过等离子体灰化和硬掩蔽技术消除MIM电容器底金属图案化期间的顶部金属角成形的方法
公开(公告)号：US06319767B1
公开(公告)日：2001-11-20
申请号：US09798639
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。第一光致抗蚀剂掩模形成在硬掩模层上。使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

3. 发明授权

US06878623B2 Technique to achieve thick silicide film for ultra-shallow junctions 失效
标题翻译：实现超浅结的厚硅化物薄膜技术
公开(公告)号：US06878623B2
公开(公告)日：2005-04-12
申请号：US10457885
申请日：2003-06-09
申请人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
发明人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/66507 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.
摘要翻译：具有相关联（LDD）区域和源极和漏极的栅极结构如常规形成。例如，沿着栅极结构的侧壁形成第一氧化物间隔物。然后在栅极结构的表面上沉积诸如钛的金属层。形成第二侧壁间隔物，覆盖第一侧壁间隔物上的金属，并将金属覆盖在隔离区上。在栅极结构的表面上沉积多晶硅层。进行快速热退火（RTA），使得金属与金属之下的结中的硅和形成金属硅化物的金属上方的多晶硅反应。沿着第一和第二侧壁间隔物之间的侧壁以及隔离区域上的金属不会反应并被蚀刻掉。通过在金属上方的多晶硅层中提供附加的硅源，可获得更厚的硅化物。

4. 发明授权

US06432797B1 Simplified method to reduce or eliminate STI oxide divots 失效
标题翻译：简化方法来减少或消除STI氧化层
公开(公告)号：US06432797B1
公开(公告)日：2002-08-13
申请号：US09768487
申请日：2001-01-25
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/31053 , H01L21/31055
摘要： A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。将氮原子注入到覆盖沟槽的氧化物层中。将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

5. 发明授权

US06303418B1 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer 有权
标题翻译：制造具有双栅极结构和高介电常数栅极绝缘体层的CMOS器件的方法
公开(公告)号：US06303418B1
公开(公告)日：2001-10-16
申请号：US09607282
申请日：2000-06-30
申请人： Cher Liang Cha , Alex See , Lap Chan
发明人： Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region. Removal of unwanted regions of metal, and of in situ polysilicon, result in the definition of a metal gate structure, on the high k gate insulator layer, in the NMOS region, and in the definition of a metal—in situ doped polysilicon gate structure, on the high k gate insulator layer, in the PMOS region, with both gate structures embedded in openings in the composite insulator layer, previously formed via removal of the silicon nitride dummy gate structures.
摘要翻译：已经开发了在用于PMOS器件的同一高k栅极绝缘体层上形成用于NMOS器件的高k栅极绝缘体层上并同时形成金属 - 多晶硅栅极结构的金属栅极结构的方法。该方法的特征是在复合绝缘体层中形成开口，通过去除嵌入复合绝缘体层中的氮化硅虚拟栅极结构，其中开口暴露用于随后的NMOS和PMOS沟道区的半导体衬底的区域。沉积高k栅极绝缘体层之后是沉积原位掺杂的多晶硅层。在去除位于NMOS区域中的原位掺杂多晶硅层的一部分之后，金属层沉积在NMOS区域中的下面的高k栅极绝缘体层上以及在PMOS区域中的原位多晶硅层上。去除金属和原位多晶硅的不需要的区域导致在NMOS区域中的高k栅极绝缘体层上以及在金属原位掺杂的多晶硅栅极结构的定义中金属栅极结构的定义在PMOS区域中的高k栅极绝缘体层上，两个栅极结构嵌入在复合绝缘体层中的开口中，预先通过去除氮化硅虚拟栅极结构而形成。

6. 发明授权

US06355563B1 Versatile copper-wiring layout design with low-k dielectric integration 失效
标题翻译：多功能铜线布局设计，低k电介质集成
公开(公告)号：US06355563B1
公开(公告)日：2002-03-12
申请号：US09798652
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
发明人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L21/76825 , H01L21/76831 , H01L21/76832
摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
摘要翻译：描述了一种将低介电常数电介质材料与铜金属化相结合的方法。金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。抛光电介质层，从而暴露虚拟通孔。此后，电介质层被固化，由此形成交联表面层。去除虚设通孔，从而将通孔的一部分氮化物层露出。去除暴露的氮化物层。通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

7. 发明授权

US06348385B1 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant 有权
标题翻译：使用具有低介电常数的原位掺杂间隔物的具有小覆盖电容的短沟道CMOS晶体管的方法
公开(公告)号：US06348385B1
公开(公告)日：2002-02-19
申请号：US09726256
申请日：2000-11-30
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/2255 , H01L21/28167 , H01L29/4983 , H01L29/51 , H01L29/66537 , H01L29/66553 , H01L29/7834
摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
摘要翻译：使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。在基板上形成虚拟栅极。使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。在源极和漏极区上的衬底上形成掩模层。我们删除虚拟门。在掩蔽层的侧壁上形成掺杂的低k间隔物。掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。我们在掩模层上形成一个高k栅介质层。在高K电介质层上形成栅极层。栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

8. 发明授权

US06558994B2 Dual silicon-on-insulator device wafer die 失效
公开(公告)号：US06558994B2
公开(公告)日：2003-05-06
申请号：US09841564
申请日：2001-03-01
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

9. 发明授权

US06849928B2 Dual silicon-on-insulator device wafer die 失效
标题翻译：双硅绝缘体上硅器件芯片
公开(公告)号：US06849928B2
公开(公告)日：2005-02-01
申请号：US10327309
申请日：2002-12-19
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L21/762 , H01L23/28
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
摘要翻译：提供一种绝缘体上半导体器件，其中单个晶片管芯在绝缘体层上包含晶体管以形成完全耗尽的绝缘体上硅器件，并且在半导体晶片上的绝缘体结构上形成半导体岛中的晶体管形成部分耗尽的绝缘体上硅器件。

10. 发明授权

US07119010B2 Integrated circuit with self-aligned line and via and manufacturing method therefor 有权
公开(公告)号：US07119010B2
公开(公告)日：2006-10-10
申请号：US10128875
申请日：2002-04-23
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

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