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1. 发明专利

TW201620389A 用於調理咖啡之自然釋放萃取法审中-公开
简体标题：用于调理咖啡之自然释放萃取法
公开(公告)号：TW201620389A
公开(公告)日：2016-06-16
申请号：TW103141995
申请日：2014-12-03
申请人：陳佳正 , CHEN, JIA ZHENG
发明人：陳佳正 , CHEN, JIA ZHENG
IPC分类号： A23F5/24 , A23F5/26
摘要：一種用於調理咖啡之自然釋放萃取法，其依序包含有一備料步驟、量測步驟、混合步驟、過濾步驟等；其中，首先該量測步驟先行該熱水之溫度調降至90~95度時，而後再將該咖啡粉置入前述降溫之熱水內，以使該咖啡粉溶解於該熱水中，且該咖啡粉溶解過程中係採用熱水特定溫度設定方式，使該咖啡粉能以最佳萃取方式，而自然地將其中之咖啡因予以釋放出，而形成一含有咖啡渣之咖啡液(即混合步驟)，之後再透過一過濾器將咖啡液之咖啡渣予以過濾去除(即過濾步驟)後，即可得到一風味極佳且可供飲用之咖啡飲品。
简体摘要：一种用于调理咖啡之自然释放萃取法，其依序包含有一备料步骤、量测步骤、混合步骤、过滤步骤等；其中，首先该量测步骤先行该热水之温度调降至90~95度时，而后再将该咖啡粉置入前述降温之热水内，以使该咖啡粉溶解于该热水中，且该咖啡粉溶解过程中系采用热水特定温度设置方式，使该咖啡粉能以最佳萃取方式，而自然地将其中之咖啡因予以释放出，而形成一含有咖啡渣之咖啡液(即混合步骤)，之后再透过一过滤器将咖啡液之咖啡渣予以过滤去除(即过滤步骤)后，即可得到一风味极佳且可供饮用之咖啡饮品。

2. 发明授权

US08728518B2 Butylphthalide self-emulsifying drug delivery system, its preparation and method and application 有权
标题翻译：丁苯酞自乳化药物输送系统，其制备方法及应用
公开(公告)号：US08728518B2
公开(公告)日：2014-05-20
申请号：US11574313
申请日：2005-08-26
申请人： Zhentao Liu , Liying Yang , Hanyu Yang , Yuqing Gao , Dongmin Shen , Wenmin Guo , Xiaolong Feng , Jia Zheng
发明人： Zhentao Liu , Liying Yang , Hanyu Yang , Yuqing Gao , Dongmin Shen , Wenmin Guo , Xiaolong Feng , Jia Zheng
IPC分类号： A61K9/66
CPC分类号： A61K9/1075 , A61K9/0095 , A61K9/1617 , A61K9/2013 , A61K9/4858 , A61K31/34
摘要： The present invention relates to a novel drug delivery and release system, i.e. Self-emulsifying Drug Delivery System (SEDDS), of butylphthalide, to a preparation process thereof, and to a use thereof in a pharmaceutical formulation. The drug delivery system comprises as essential ingredients 1% to 65% of butylphthalide and 10% to 65% of a emulsifying agent, together with various excipients as required depending on the desired dosage forms. The present invention significantly increases the contact area between butylphthalide and the mucous membrane of the gastrointestinal tract, and therefore improves the absorptivity of the drug.
摘要翻译：本发明涉及一种新型药物递送和释放系统，即丁基苯酞的自乳化药物递送系统（SEDDS），其制备方法及其在药物制剂中的用途。药物递送系统根据所需的剂型，根据需要含有1％至65％的丁基苯酞和10％至65％的乳化剂，以及各种赋形剂。本发明显着增加了丁基苯酞与胃肠道粘膜之间的接触面积，从而提高了药物的吸收性。

3. 发明申请

US20080319056A1 Butylphthalide Self-Emulsifying Drug Delivery System, Its Preparation Method and Application 有权
标题翻译：丁苯酞自乳化药物输送系统及其制备方法与应用
公开(公告)号：US20080319056A1
公开(公告)日：2008-12-25
申请号：US11574313
申请日：2005-08-26
申请人： Zhentao Liu , Liying Yang , Hanyu Yang , Yuqing Gao , Dongmin Shen , Wenmin Guo , Xiaolong Feng , Jia Zheng
发明人： Zhentao Liu , Liying Yang , Hanyu Yang , Yuqing Gao , Dongmin Shen , Wenmin Guo , Xiaolong Feng , Jia Zheng
IPC分类号： A61K31/343 , A61P43/00
CPC分类号： A61K9/1075 , A61K9/0095 , A61K9/1617 , A61K9/2013 , A61K9/4858 , A61K31/34
摘要： The present invention relates to a novel drug delivery and release system, i.e. Self-emulsifying Drug Delivery System (SEDDS), of butylphthalide, to a preparation process thereof, and to a use thereof in a pharmaceutical formulation. The drug delivery system comprises as essential ingredients 1% to 65% of butylphthalide and 10% to 65% of a emulsifying agent, together with various excipients as required depending on the desired dosage forms. The present invention significantly increases the contact area between butylphthalide and the mucous membrane of the gastrointestinal tract, and therefore improves the absorptivity of the drug.
摘要翻译：本发明涉及一种新型药物递送和释放系统，即丁基苯酞的自乳化药物递送系统（SEDDS），其制备方法及其在药物制剂中的用途。药物递送系统根据所需的剂型，根据需要含有1％至65％的丁基苯酞和10％至65％的乳化剂，以及各种赋形剂。本发明显着增加了丁基苯酞与胃肠道粘膜之间的接触面积，从而提高了药物的吸收性。

4. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

5. 发明申请

US20050145953A1 Heterojunction BiCMOS integrated circuits and method therefor 审中-公开
标题翻译：异质结BiCMOS集成电路及其方法
公开(公告)号：US20050145953A1
公开(公告)日：2005-07-07
申请号：US10752454
申请日：2004-01-05
申请人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
发明人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L31/113
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.
摘要翻译：一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。提供衬底，并且在衬底上形成多晶硅层。栅极结构和非本征基极结构形成在多晶硅层中。多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

6. 发明申请

US20050101102A1 Non-volatile memory and manufacturing method using STI trench implantation 有权
标题翻译：使用STI沟槽植入的非易失性存储器和制造方法
公开(公告)号：US20050101102A1
公开(公告)日：2005-05-12
申请号：US10703289
申请日：2003-11-06
申请人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
发明人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76237 , H01L27/115 , H01L29/66825
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.
摘要翻译：一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。植入的源极区域形成在有源区域的一侧的沟槽中的一个中。在有源区的另一侧的另一个沟槽中形成注入的漏极区。然后在沟槽中形成浅沟槽隔离。在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

7. 发明申请

US20050101096A1 SELF-ALIGNED LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：自对准侧向异相双极晶体管
公开(公告)号：US20050101096A1
公开(公告)日：2005-05-12
申请号：US10703284
申请日：2003-11-06
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

8. 发明申请

US20050085056A1 Integrated circuit with protected implantation profiles and method for the formation thereof 有权
标题翻译：具有保护注入轮廓的集成电路及其形成方法
公开(公告)号：US20050085056A1
公开(公告)日：2005-04-21
申请号：US10689923
申请日：2003-10-17
申请人： Tommy Lai , Pradeep Ramachandramurthy Yelehanka , Jia Zheng , Weining Li
发明人： Tommy Lai , Pradeep Ramachandramurthy Yelehanka , Jia Zheng , Weining Li
IPC分类号： H01L21/3115 , H01L21/314 , H01L21/8239 , H01L21/8247 , H01L21/425 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译：一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

9. 发明申请

US20050009357A1 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US20050009357A1
公开(公告)日：2005-01-13
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
发明人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

10. 发明申请

US20060207965A1 Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits 有权
标题翻译：在同一电介质区域上形成高k和低k材料的方法及其在混合模式电路中的应用
公开(公告)号：US20060207965A1
公开(公告)日：2006-09-21
申请号：US11438188
申请日：2006-05-22
申请人： Yelehanka Ramaghandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zheng , Purakh Verma
发明人： Yelehanka Ramaghandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zheng , Purakh Verma
IPC分类号： H01B13/00
CPC分类号： H01L28/55 , H01L21/02109 , H01L21/3127 , H01L21/3144 , H01L21/31625 , H01L21/31629 , H01L27/0617 , H01L27/0629 , H01L27/1203 , H01L2924/0002 , Y10T428/12035 , H01L2924/00
摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a a layer of choice.
摘要翻译：一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

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