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1. 发明申请

WO2020169941A1 METHOD AND DEVICE FOR MEASURING A PULSE SIGNAL WITH HIGH DYNAMIC RANGE 审中-公开
公开(公告)号：WO2020169941A1
公开(公告)日：2020-08-27
申请号：PCT/GB2020/000016
申请日：2020-02-18
申请人： THE SECRETARY OF STATE FOR DEFENCE
发明人： HILLIER, David lanto , WINTER, David Norman
IPC分类号： G01J11/00 , G01R29/02 , G01S7/486 , H01S3/00 , H03K5/13
摘要： The invention relates to devices and methods of characterising a single unknown pulse signal. They create multiple replica of the original that may be more reliably measured, by dividing the signal through nodes and using different signal pathways that may apply a temporal delay. The device and methods have multiple fields of application, most notably with the internal confinement fusion industry.

2. 发明申请

WO2018023919A1 一种阶数大于1的大功率可调高频分数阶电容及其控制方法审中-公开
公开(公告)号：WO2018023919A1
公开(公告)日：2018-02-08
申请号：PCT/CN2016/110552
申请日：2016-12-17
申请人：华南理工大学
发明人：张波 , 江彦伟
IPC分类号： H03K5/13 , H03K7/08
CPC分类号： H03K7/08 , H02M7/537 , H02M7/538 , H02M2001/0012 , H02M2007/4815 , H03K5/13 , Y02B70/1441
摘要：一种阶数大于1的大功率可调高频分数阶电容及其控制方法，分数阶电容包括交流输入模块(1)、耦合阻抗(2)、高频交流受控电压源(3)、交流输入采样模块(4)、控制器(5)。控制器(5)根据交流输入采样模块(4)采集到的输入电压信号和输入电流信号，产生相应的控制信号，控制受控电压源(3)的输出电压，使输入电流和输入电压之间符合分数阶电容的电流电压关系。可调高频分数阶电容，可工作在输入电压即分数阶电容电压为高频的时候，所得到的输入电流输入电压之间的关系在所需工作频率处与阶数大于1的分数阶电容的定义完全一致，还可以通过调整控制器的参数，灵活调节实现不同分数阶电容的阶数和容值，还可选用不同功率等级的受控电压源以适应不同的功率应用场合。

3. 发明申请

WO2016190956A1 AREA-EFFICIENT METAL-PROGRAMMABLE PULSE LATCH DESIGN 审中-公开
标题翻译：区域有效的金属可编程脉冲锁定设计
公开(公告)号：WO2016190956A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/025180
申请日：2016-03-31
申请人： QUALCOMM INCORPORATED
发明人： YE, Qi , DILLEN, Steven James , DATTA, Animesh , DUAN, Zhengyu , SAHU, Satyanarayana , NARENDRANATH, Praveen
IPC分类号： H03K3/012 , H03K3/037 , H03K5/13
CPC分类号： H03K3/0375 , H03K3/012 , H03K3/037 , H03K5/131
摘要： A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally (Formula (A) at a delay module output, where I 1 is a function of I and I A is a function of I N 0 and B 0, and where I is a delay module input, B 0 is a first input bit, and I N0 is a first net input.
摘要翻译：脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。延迟模块在功能上提供（延迟模块输出中的公式（A）），其中I 1是I的函数，IA是IN 0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，而N0是第一个净输入。

4. 发明申请

WO2016071813A3 DIGITALLY CONTROLLED OSCILLATOR (DCO) ARCHITECTURE 审中-公开
标题翻译：数字控制振荡器（DCO）架构
公开(公告)号：WO2016071813A3
公开(公告)日：2016-06-30
申请号：PCT/IB2015058390
申请日：2015-10-30
申请人： ISTITUTO NAZ DI FISICA NUCLEARE
发明人： GIORDANO RAFFAELE , CADEDDU SANDRO , ALOISIO ALBERTO , AMELI FABRIZIO , BOCCI VALERIO , IZZO VINCENZO , LAI ADRIANO , MASTROIANNI STEFANO
IPC分类号： H03K5/13 , G06F1/10 , H03K5/15 , H04L7/033
CPC分类号： H03K5/133 , G06F1/10 , H03K5/1504 , H03K2005/00097 , H03K2005/00234 , H04L7/033 , H04L7/0331
摘要： A digitally controlled oscillator architecture is natively digital and therefore not dependent upon any particular technology process for the manufacture thereof, and basically it comprises: a chain of delay elements having each at least three inputs and an output, a first input driven by the output of the previous element and used for propagation in the line, a second input for the injection of a signal in the line and a third input or inputs for the selection of the behaviour of each delay element; and a high fan-out network to drive with balanced delays the injection inputs of said delay elements, wherein said high fan out network is based on a clock tree, which distributes the input signal to the second input of each delay element.
摘要翻译：数字控制振荡器架构是本地数字的，因此不依赖于用于其制造的任何特定技术过程，并且其基本上包括：具有每个至少三个输入和输出的延迟元件链，由输出驱动的第一输入前一个元件并用于在线路中的传播，用于在该线路中注入信号的第二输入端和用于选择每个延迟元件的行为的第三输入端或输入端; 以及高扇出网络，以均衡延迟来驱动所述延迟元件的注入输入，其中所述高扇出输出网络基于时钟树，时钟树将输入信号分配给每个延迟元件的第二输入。

5. 发明申请

WO2016071813A2 DIGITALLY CONTROLLED OSCILLATOR (DCO) ARCHITECTURE 审中-公开
标题翻译：数字控制振荡器（DCO）体系结构
公开(公告)号：WO2016071813A2
公开(公告)日：2016-05-12
申请号：PCT/IB2015/058390
申请日：2015-10-30
申请人： ISTITUTO NAZIONALE DI FISICA NUCLEARE
发明人： GIORDANO, Raffaele , CADEDDU, Sandro , ALOISIO, Alberto , AMELI, Fabrizio , BOCCI, Valerio , IZZO, Vincenzo , LAI, Adriano , MASTROIANNI, Stefano
IPC分类号： H03K5/13 , H03K5/15 , G06F1/10 , H04L7/033
CPC分类号： H03K5/133 , G06F1/10 , H03K5/1504 , H03K2005/00097 , H03K2005/00234 , H04L7/033 , H04L7/0331
摘要： A digitally controlled oscillator architecture is natively digital and therefore not dependent upon any particular technology process for the manufacture thereof, and basically it comprises: a chain of delay elements having each at least three inputs and an output, a first input driven by the output of the previous element and used for propagation in the line, a second input for the injection of a signal in the line and a third input or inputs for the selection of the behaviour of each delay element; and a high fan-out network to drive with balanced delays the injection inputs of said delay elements, wherein said high fan out network is based on a clock tree, which distributes the input signal to the second input of each delay element.
摘要翻译：数字控制振荡器架构本身是数字的，因此不依赖于用于其制造的任何特定工艺过程，并且基本上包括：延迟元件链，每个延迟元件具有至少三个输入端和输出端，由前一元件的输出驱动并用于在该行中传播的第一输入，用于在该行中注入信号的第二输入和用于选择每个延迟元件的行为的第三输入或输入; 以及高扇出网络，以平衡的延迟驱动所述延迟元件的注入输入，其中所述高扇出网络基于时钟树，所述时钟树将输入信号分配给每个延迟元件的第二输入端。 >

6. 发明申请

WO2016036572A2 DELAY CIRCUITS AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：延迟电路及相关系统和方法
公开(公告)号：WO2016036572A2
公开(公告)日：2016-03-10
申请号：PCT/US2015/047153
申请日：2015-08-27
申请人： QUALCOMM INCORPORATED
发明人： AMARILIO, Lior , GOLUBITSKI, Alexander , HALLER, Haim, Hagay , KOLMAKOV, Felix , STHOEGER, Gilad
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , G06F1/10 , G06F13/4068 , G06F13/4221 , G11C19/00 , H03K5/13 , H03K2005/0015 , Y02D10/14 , Y02D10/151
摘要： Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.
摘要翻译：公开了延迟电路以及相关的系统和方法。在一个方面，提供了一种延迟电路，其使用逻辑来准确地延迟输出使能信号以减少或避免从属装置内的数据危险。延迟电路包括两个移位寄存器链，其被配置为基于慢时钟来接收输出使能信号。第一移位寄存器链由快时钟的上升沿计时，并提供第一选通信号。第二个移位寄存器链由快速时钟的下降沿提供时钟，并提供第二个选通信号。该逻辑使用第一和第二选通信号以及输出使能信号来提供延迟的输出使能输出信号。延迟电路为输出使能信号提供高度精确的时间延迟，从而减少或避免区域中的数据危险和节能方式。

7. 发明申请

WO2015183584A1 RECONFIGURABLE FREQUENCY DIVIDER 审中-公开
标题翻译：可重构频率分频器
公开(公告)号：WO2015183584A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/030883
申请日：2015-05-14
申请人： QUALCOMM INCORPORATED
发明人： PAI, Hung-Chuan , ZHANG, Gang
IPC分类号： H03L7/16 , H03L7/081 , H03K5/00 , H03K5/13
CPC分类号： H03K21/02 , H03K5/00006 , H03K5/133 , H03K23/667 , H03L7/081 , H03L7/16 , H04B1/40
摘要： Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.
摘要翻译：提供可重构分频器电路的方面。可重构分频器可以包括被配置为接收输入信号的分频器。分频器还可以包括被配置为接收由分频器产生的分频信号的延迟电路。分频器还可以包括被配置为基于由延迟电路产生的延迟信号产生输出信号的倍频器，其中延迟电路被配置为接收输出信号。

8. 发明申请

WO2014059172A3 DIGITALLY CONTROLLED DELAY LINE FOR A STRUCTURED ASIC HAVING VIA CONFIGURABLE FABRIC FOR HIGH-SPEED INTERFACE 审中-公开
标题翻译：用于高速接口的具有可配置织物的结构化ASIC的数字控制延迟线
公开(公告)号：WO2014059172A3
公开(公告)日：2014-07-24
申请号：PCT/US2013064383
申请日：2013-10-10
申请人： EASIC CORP
发明人： ANDREEV ALEXANDER , GRIBOK SERGEY , SERBAN MARIAN , VERITA MASSIMO , SIM KEE-WEI , LEW KOK-HIN
IPC分类号： H03K5/13
CPC分类号： H03H17/0009 , H03H11/265 , H03K5/131 , H03K2005/00065
摘要： A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL.
摘要翻译：用于结构化ASIC芯片的数字控制延迟线（DCDL）用于将输入或输出信号延迟进入或离开结构化ASIC中的核心逻辑。 DCDL具有多级配置，其在优选实施例中包括两个精细延迟级，用于通过逆变器使用子栅极延迟来微调延迟，所述逆变器的延迟可以利用并联CMOS晶体管来调整，所述并联CMOS晶体管的栅极被电压控制信号是温度计编码。微调阶段之后是使用门级延迟的粗略延迟阶段。 DCDL控制器输出格雷编码的控制信号并通过二进制到温度计解码器转换为温度计编码的控制信号。 DCDL电路模块和随附的结构化ASIC是在28 nm CMOS工艺光刻节点或更小的节点上制造的。 DCDL采用了使用平衡二叉树的高速路由结构。

9. 发明申请

WO2013026040A8 SYSTEM FOR CLOCKING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：闭合集成电路的系统
公开(公告)号：WO2013026040A8
公开(公告)日：2013-08-08
申请号：PCT/US2012051479
申请日：2012-08-17
申请人： BROADCOM CORP , SIPPEL TIM
发明人： SIPPEL TIM
IPC分类号： H03K3/03 , G06F1/04 , H03K3/037 , H03K5/13
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
摘要翻译：实施例提供了用于基于IC电源电压来动态地调节集成电路（IC）的时钟频率的系统和方法。通过这样做，时钟频率不再受最坏情况电压电平的约束，并且可以支持更高的有效时钟频率，从而提高了IC性能。实施例包括波时钟系统，其使用被配置为基本上匹配IC的相应逻辑路径的延迟的多个延迟链。随着逻辑路径的延迟随着电源电压和温度的变化而变化，与逻辑路径匹配的延迟链经历基本类似的改变，并用于调节IC的时钟频率。

10. 发明申请

WO2012167239A3 APPARATUS AND SYSTEMS DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY 审中-公开
标题翻译：具有改进线性的装置和系统数字相位插值器
公开(公告)号：WO2012167239A3
公开(公告)日：2013-04-25
申请号：PCT/US2012040718
申请日：2012-06-04
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , ERDOGAN MUSTAFA ULVI
发明人： ERDOGAN MUSTAFA ULVI
IPC分类号： H03L7/081 , H03K5/13
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00052 , H03L7/0812 , H03L7/16
摘要： An apparatus comprising: a first control switch (111) driven by a first bit value; a first weighted switch (141) driven by a first clock signal; a first intermediate node (112) coupled between the first control switch and the first weighted switch; a first pre-charge transistor (131) coupled to the first intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal; a second control switch (121) driven by an inverse of the bit; a second weighted switch (151) driven by a second clock signal; a second intermediate node (122) coupled between the second control switch and the second weighted switch; a second pre-charge transistor (135) coupled to the second intermediate node, wherein the second pre-charge transistor (135) is driven by an inverse of the second clock signal; and a capacitor (159) coupled to the first control switch, the second control switch, the first weighted switch and the second weighted switch.
摘要翻译：一种装置，包括：由第一位值驱动的第一控制开关（111）由第一时钟信号驱动的第一加权开关（141）耦合在所述第一控制开关和所述第一加权开关之间的第一中间节点（112）耦合到所述第一中间节点的第一预充电晶体管（131），其中所述预充电晶体管由所述时钟信号的反相驱动; 由比特的倒数驱动的第二控制开关（121）由第二时钟信号驱动的第二加权开关（151）; 耦合在所述第二控制开关和所述第二加权开关之间的第二中间节点（122）耦合到所述第二中间节点的第二预充电晶体管（135），其中所述第二预充电晶体管（135）由所述第二时钟信号的反相驱动; 以及耦合到第一控制开关，第二控制开关，第一加权开关和第二加权开关的电容器（159）。

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