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1. 发明申请

WO2020172050A1 METHODS AND APPARATUS TO IMPROVE PERFORMANCE WHILE READING A ONE-TIME-PROGRAMMABLE MEMORY 审中-公开
公开(公告)号：WO2020172050A1
公开(公告)日：2020-08-27
申请号：PCT/US2020/018234
申请日：2020-02-14
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： BALASUBRAMANIAN, Suresh , SPRIGGS, Stephen Wayne , JAMISON, George B.
IPC分类号： G11C11/407 , G11C17/08
摘要： Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. An example method includes initializing an output (288) of a sensing circuit (218) to be a first logic high value, obtaining, from the memory (202 or 204), a first current ( IBIT ) corresponding to a memory bit stored in the memory (202 or 204), replicating the first current (I BIT ), determining whether the replicated first current (I BIT ) is greater than a second current (I REF ), and in response to determining that the replicated first current (I BIT ) is greater than the second current (I REF ), generating a second logic high value at the output (288) of the sensing circuit (218).

2. 发明申请

WO02043152A2 POLY FUSE ROM WITH MOS DEVICE BASED CELL STRUCTURE AND THE METHOD FOR READ AND WRITE THEREFORE 审中-公开
标题翻译：具有基于MOS器件的细胞结构的POLY FUSE ROM及其读取和写入方法
公开(公告)号：WO02043152A2
公开(公告)日：2002-05-30
申请号：PCT/EP2001/013467
申请日：2001-11-19
IPC分类号： G11C17/08 , G11C17/16 , G11C17/18 , H01L21/8246 , H01L23/482 , H01L23/525 , H01L27/02 , H01L27/10 , H01L27/112
CPC分类号： G11C17/18 , G11C17/16 , H01L23/4824 , H01L23/525 , H01L23/5256 , H01L27/0207 , H01L27/112 , H01L27/11206 , H01L27/1122 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A one-time programmable (OTP) structure is implemented using a self-aligned silicided (SALICIDE) poly-silicon fuse. In an example embodiment, the OTP structure is laid out as a fuse element having a first terminal and a second terminal. A switching transistor having a drain, source, and a gate surrounds the fuse element. The drain is coupled to the second terminal of the fuse element surrounds the fuse element. The gate surrounds the drain. The source surrounds the gate. To build transistor with sufficient drive capability for programming the fuse element, the geometry of the gate is laid out in a serpentine or an equivalent pattern increase the effective W/L. A feature of this layout is that OTP cells may be abutted to one-another to form an array. Metallization is arranged so that row lines connect to the first terminal of the fuse element and column lines connect to the gate of the switching transistor. The arrangement enables the placing of read and write circuits at opposite sides of the array. All of the gates in a column may be read simultaneously while providing write current to program one fuse at a time.
摘要翻译：使用自对准硅化物（SALICIDE）多晶硅保险丝实现一次性可编程（OTP）结构。在示例性实施例中，OTP结构被布置为具有第一端子和第二端子的熔丝元件。具有漏极，源极和栅极的开关晶体管围绕熔丝元件。漏极耦合到熔丝元件的第二端围绕熔丝元件。门围绕排水沟。源围绕着门。为了构建具有足够驱动能力的晶体管来编程熔丝元件，栅极的几何形状以蛇形或等效图案布置，增加了有效的W / L。该布局的特征是OTP单元可以彼此邻接以形成阵列。金属化被布置成使得行线连接到熔丝元件的第一端子，列线连接到开关晶体管的栅极。该布置使得能够在阵列的相对侧放置读取和写入电路。同时可以同时读取列中的所有门，同时提供写入电流一次编程一个保险丝。

3. 发明申请

WO0191185A3 ULTRA-LATE PROGRAMMING ROM AND METHOD OF MANUFACTURE 审中-公开
标题翻译：超级编程ROM和制造方法
公开(公告)号：WO0191185A3
公开(公告)日：2002-03-28
申请号：PCT/US0111878
申请日：2001-04-11
申请人： MOTOROLA INC
发明人： PARRIS PATRICE , MORTON BRUCE L , CIOSEK WALTER J , AURORA MARK , SMITH ROBERT
IPC分类号： G11C17/08 , G11C11/56 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide "1" outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide "0" outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享端子，由此相邻的晶体管共享源极和漏极中的一个。多个接触线，一个连接到每个公共端子的接触线用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供来自所选单元的“0”输出。

4. 发明申请

WO2019040503A1 SELF-REFERENCING MEMORY DEVICE 审中-公开
公开(公告)号：WO2019040503A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/047338
申请日：2018-08-21
申请人： MICRON TECHNOLOGY, INC.
发明人： MUZZETTO, Riccardo
IPC分类号： G11C17/08 , G11C17/18
摘要： Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self- referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

5. 发明申请

WO2017168130A1 ONE-TIME AND MULTI-TIME PROGRAMING USING A CORRELATED ELECTRON SWITCH 审中-公开
标题翻译：一次和多次编程使用相关的电子开关
公开(公告)号：WO2017168130A1
公开(公告)日：2017-10-05
申请号：PCT/GB2017/050837
申请日：2017-03-24
申请人： ARM LTD
发明人： SHIFREN, Lucian , AITKEN, Robert Campbell , CHANDRA, Vikas , SANDHU, Bal S
IPC分类号： G11C13/00 , G11C17/08 , G11C17/16 , G11C17/18
CPC分类号： G11C7/00 , G11C13/0007 , G11C13/0035 , G11C13/0069 , G11C17/08 , G11C17/16 , G11C17/18 , G11C2013/0078 , G11C2013/009 , G11C2213/15
摘要： An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.
摘要翻译：提供了一种包括相关电子开关（CES）元件和编程电路的装置。编程电路向CES元件提供编程信号，以在CES元件被编程的次数小于阈值时将CES元件编程为多个阻抗状态的阻抗状态。

6. 发明申请

WO2008005919A3 HIGH SPEED READ-ONLY MEMORY 审中-公开
标题翻译：高速只读存储器
公开(公告)号：WO2008005919A3
公开(公告)日：2008-07-24
申请号：PCT/US2007072639
申请日：2007-07-02
申请人： TEXAS INSTRUMENTS INC , BALASURAMANIAN SURESH
发明人： BALASURAMANIAN SURESH
IPC分类号： G11C17/08 , G11C17/00
CPC分类号： G11C7/02 , G11C7/062 , G11C17/12
摘要： A high speed read-only memory (ROM) (200). Data stored in a memory cell in the ROM array is provided to a sense amplifier in a differential form. Two transistors storing complementary logic states form a memory cell and store a data bit. One transistor has a source terminal connected to a ground terminal while the other transistor has a source terminal left unconnected. The drain terminals of each of the two transistors is connected to a corresponding one of a differential bit- line pair which provides a differential signal representing the stored data bit to a sense amplifier (245).
摘要翻译：高速只读存储器（ROM）（200）。存储在ROM阵列中的存储单元中的数据以差分形式提供给读出放大器。存储互补逻辑状态的两个晶体管形成存储器单元并存储数据位。一个晶体管的源极端子连接到接地端子，而另一个晶体管的源极端子未连接。两个晶体管中的每一个的漏极端子连接到差分比特线对中的相应一个，差分比特线对将表示存储的数据比特的差分信号提供给读出放大器（245）。

7. 发明申请

WO0243152A3 POLY FUSE ROM 审中-公开
公开(公告)号：WO0243152A3
公开(公告)日：2002-09-19
申请号：PCT/EP0113467
申请日：2001-11-19
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： KHOURY ELIE G
IPC分类号： G11C17/08 , G11C17/16 , G11C17/18 , H01L21/8246 , H01L23/482 , H01L23/525 , H01L27/02 , H01L27/10 , H01L27/112
CPC分类号： G11C17/18 , G11C17/16 , H01L23/4824 , H01L23/525 , H01L23/5256 , H01L27/0207 , H01L27/112 , H01L27/11206 , H01L27/1122 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A one-time programmable (OTP) structure is implemented using a self-aligned silicided (SALICIDE) poly-silicon fuse. In an example embodiment, the OTP structure is laid out as a fuse element having a first terminal and a second terminal. A switching transistor having a drain, source, and a gate surrounds the fuse element. The drain is coupled to the second terminal of the fuse element surrounds the fuse element. The gate surrounds the drain. The source surrounds the gate. To build transistor with sufficient drive capability for programming the fuse element, the geometry of the gate is laid out in a serpentine or an equivalent pattern increase the effective W/L. A feature of this layout is that OTP cells may be abutted to one-another to form an array. Metallization is arranged so that row lines connect to the first terminal of the fuse element and column lines connect to the gate of the switching transistor. The arrangement enables the placing of read and write circuits at opposite sides of the array. All of the gates in a column may be read simultaneously while providing write current to program one fuse at a time.
摘要翻译：使用自对准硅化物（SALICIDE）多晶硅保险丝实现一次性可编程（OTP）结构。在示例性实施例中，OTP结构被布置为具有第一端子和第二端子的熔丝元件。具有漏极，源极和栅极的开关晶体管围绕熔丝元件。漏极耦合到熔丝元件的第二端围绕熔丝元件。门围绕排水沟。源围绕着门。为了构建具有足够驱动能力的晶体管来编程熔丝元件，栅极的几何形状以蛇形或等效图案布置，增加了有效的W / L。该布局的特征是OTP单元可以彼此邻接以形成阵列。金属化被布置成使得行线连接到熔丝元件的第一端子，列线连接到开关晶体管的栅极。该布置使得能够在阵列的相对侧放置读取和写入电路。同时可以同时读取列中的所有门，同时提供写入电流一次编程一个保险丝。

8. 发明申请

WO2009121182A1 LOW THRESHOLD VOLTAGE ANTI-FUSE DEVICE 审中-公开
标题翻译：低电压电压保险丝装置
公开(公告)号：WO2009121182A1
公开(公告)日：2009-10-08
申请号：PCT/CA2009/000429
申请日：2009-04-03
申请人： SIDENSE CORP. , KURJANOWICZ, Wlodek
发明人： KURJANOWICZ, Wlodek
IPC分类号： G11C17/16 , G11C17/08
CPC分类号： H01L27/101 , H01L23/5252 , H01L27/0207 , H01L27/11206 , H01L29/42368 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.
摘要翻译：提出了具有独立于核心电路工艺制造技术的具有低阈值电压的抗熔丝器件的一次性可编程存储器单元。具有传输晶体管和反熔丝器件的双晶体管存储单元或具有双厚度栅极氧化物的单晶体管存储单元形成在为高压晶体管形成的高电压阱中。反熔丝器件的阈值电压与存储器件的核心电路中的任何晶体管的阈值电压不同，但是其栅极氧化物厚度与核心电路中的晶体管相同。传输晶体管具有与核心电路中的任何晶体管的阈值电压不同的阈值电压，并且具有与核心电路中的任何晶体管不同的栅极氧化物厚度。通过省略用于在I / O电路中制造的高电压晶体管的部分或全部阈值调整植入物来降低反熔丝器件的阈值电压。

9. 发明申请

WO01091185A2 ULTRA-LATE PROGRAMMING ROM AND METHOD OF MANUFACTURE 审中-公开
标题翻译：超级编程ROM和制造方法
公开(公告)号：WO01091185A2
公开(公告)日：2001-11-29
申请号：PCT/US2001/011878
申请日：2001-04-11
IPC分类号： G11C17/08 , G11C11/56 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide "1" outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide "0" outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享端子，由此相邻的晶体管共享源极和漏极中的一个。多个接触线，一个连接到每个公共端子的接触线用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供来自所选单元的“0”输出。

10. 发明申请

WO01084632A1 ONE-TIME UV-PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF PROGRAMMING SUCH A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：一次UV可编程非挥发性半导体存储器和编程这种半导体存储器的方法
公开(公告)号：WO01084632A1
公开(公告)日：2001-11-08
申请号：PCT/EP2001/004327
申请日：2001-04-13
IPC分类号： G11C17/08 , G11C16/18 , G11C17/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/18 , H01L27/115
摘要： One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain region (12) and a channel region (13) formed in a surface region (11) of a semiconductor substrate (10). Said semiconductor regions adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.
摘要翻译：一次性UV可编程只读存储器（1）包括以行和列为矩阵排列的MOS晶体管（T）形式的多个存储器单元，每个晶体管包括源极和漏极区域（12））和形成在半导体衬底（10）的表面区域（11）中的沟道区（13）。所述半导体区域邻接在半导体衬底的表面上形成层结构（17）的表面（14），其包括浮动栅极（16）和控制栅极（15）。层结构设置有窗口（18），UV辐射可以通过该窗口到达浮动门的边缘。存储器还设置有用于在通过UV辐射对存储器进行编程期间在衬底（10）和控制栅极（16）之间产生电压的装置。因此，可以在编程期间对存储器进行编程而不会被外部接触。

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