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1. 发明申请

WO1997020389A1 LOW VOLTAGE LOGIC CIRCUIT 审中-公开
标题翻译：低电压逻辑电路
公开(公告)号：WO1997020389A1
公开(公告)日：1997-06-05
申请号：PCT/IB1996001123
申请日：1996-10-21
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , MARTIN, Brian, C.
IPC分类号： H03K17/04
CPC分类号： H03K19/09448 , H03K19/013
摘要： A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device (N1) which allows the pull-down device (Q2) of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device (N1) conducts current between the input terminal (412) of the logic device and the pull-down device (Q2) when the output signal equals a certain value.
摘要翻译：提供了具有较低驱动和低速电压的BiCMOS逻辑电路。逻辑电路包括开关装置（N1），其允许逻辑电路的下拉装置（Q2）直接由输入信号驱动，而不必首先切换MOS装置。当输出信号等于某一值时，开关装置（N1）在逻辑装置的输入端（412）和下拉装置（Q2）之间传导电流。

2. 发明申请

WO1991018448A1 BiCMOS DIGITAL DRIVER CIRCUIT 审中-公开
标题翻译： BiCMOS数字驱动电路
公开(公告)号：WO1991018448A1
公开(公告)日：1991-11-28
申请号：PCT/US1991003192
申请日：1991-05-08
申请人： SIARC
发明人： SIARC , EL GAMAL, Abbas
IPC分类号： H03K19/01
CPC分类号： H03K19/09448
摘要： In one embodiment of the invention, a CMOS device (32) inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor (Q3) whose collector is coupled to a positive power supply voltage. The input signal coupled to the input of the CMOS device is also coupled to the gate of a large N-channel MOSFET (Q4) having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground. The common node (36) of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver. This driver uses much less area than a standard two-bipolar transistor BiCMOS driver with substantially equal performance.

3. 发明申请

WO1983000407A1 MONOLITHICALLY MERGED FIELD EFFECT TRANSISTOR AND BIPOLAR JUNCTION TRANSISTOR 审中-公开
标题翻译：单相合并场效应晶体管和双极晶体管晶体管
公开(公告)号：WO1983000407A1
公开(公告)日：1983-02-03
申请号：PCT/US1982000997
申请日：1982-07-20
申请人： INTERSIL, INC.
发明人： INTERSIL, INC. , ZOMMER, Nathan
IPC分类号： H01L27/02
CPC分类号： H03K19/09448 , H01L27/0716 , H01L29/7302 , H01L29/7322 , H01L29/7395
摘要： Semiconductor device comprising a monolithically merged field-effect transistor and bipolar junction transistor. The device has a semiconductor region (28a) with a base contact (13) and a gate electrode (15) such that a signal applied to the base contact (13) causes the device to function as a bipolar junction transistor, while a signal applied to the gate electrode (15) causes the device to function as a field-effect transistor. In this manner, the mode of operation may be chosen so as to achieve the most desired operating characteristics.
摘要翻译：半导体器件包括单片合并的场效应晶体管和双极结型晶体管。器件具有带有基极触点（13）和栅电极（15）的半导体区域（28a），使得施加到基极触点（13）的信号使该器件用作双极结型晶体管，同时施加信号到栅电极（15）使得器件用作场效应晶体管。以这种方式，可以选择操作模式以便实现最期望的操作特性。

4. 发明申请

WO00011788A2 DRIVING CIRCUIT 审中-公开
标题翻译：驱动电路
公开(公告)号：WO00011788A2
公开(公告)日：2000-03-02
申请号：PCT/DE1999/002416
申请日：1999-08-02
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/00315 , H03K19/017518 , H03K19/09448
摘要： The invention relates to a driving circuit comprising a driver control circuit, a first and a second driving transistor and a current limiting device. In order to limit the current flowing through the driving transistor, said current limiting device controls the voltage at the gate of said first driving transistor. A control input of the current limiting device is used to adjust the current-limitation application point to the load to be controlled by a negative feedback. According to a second embodiment, a driving circuit having one of its two transistors designed as a MOSFET and the other one as a bipolar transistor is produced in such a way that diodes of the two driving transistors block the switched-off supply voltage or transmit the voltage according to a voltage applied on the output of said driving circuit.
摘要翻译：本发明涉及具有驱动器驱动器，第一和第二驱动器晶体管以及限流装置的驱动器电路。为了限制流经第一驱动晶体管的电流，限流装置控制第一驱动晶体管的控制端的电压。通过电流限制器装置的控制输入，电流限制的起始点可以适应负载通过负反馈来驱动。本发明的第二实施例涉及在一个MOSFET的两个驱动器晶体管，另一个为双极型晶体管中的一个被执行的驱动电路，从而使两个驱动器晶体管的二极管以阻断或导通，当电源电压，并且根据一个在驱动器电路的电压的输出施加。

5. 发明申请

WO1993008523A2 1-BIT ADDER AND MULTIPLIER CONTAINING A 1-BIT ADDER 审中-公开
标题翻译：包含1位加法器的1位加法器和乘法器
公开(公告)号：WO1993008523A2
公开(公告)日：1993-04-29
申请号：PCT/EP1992002350
申请日：1992-10-12
申请人： THOMSON CONSUMER ELECTRONICS S.A. , CHAN YAN FONG, Joseph
发明人： THOMSON CONSUMER ELECTRONICS S.A.
IPC分类号： G06F07/50
CPC分类号： G06F7/5338 , G06F7/501 , G06F7/507 , G06F2207/3884 , G06F2207/4812 , G06F2207/4816 , H03K19/09448
摘要： E.g. for video applications fast multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough. The inventive multiplier in nearly full CMOS design has been constructed with a 1.2 mu BICMOS technology, having a multiplication time of 9 ns with a supply voltage of 5 volts. Minimum multiplication time has been achieved by a combination of the following techniques: use of the Booth-Mc Sorley algorithm in order to reduce the number of partial products; diagonal propagation of the carry from one partial product to the other allowing all the sums on one line to be done simultaneously; use of the carry select approach in the final 14 bits adder and in the first two adders in the intermediate rows; use of inventive fast one-bit full adders with complementary pass transistor logic.
摘要翻译：例如。对于视频应用，需要具有高分辨率的快速乘法器。但是更高的分辨率导致更多的部分产品被内部计算。可以使用Booth-Mc Sorley算法来减少所需数量的这种部分产品。该算法可以与进位从一个部分乘积到另一个的对角线传播组合，允许同时计算一条线上的所有和。但可达乘法时间不够短。几乎全CMOS设计中的创造性乘法器已经用1.2微米的BICMOS技术构建，具有9ns的乘法时间，电源电压为5伏。通过以下技术的组合实现了最小乘法时间：使用Booth-Mc Sorley算法来减少部分乘积; 进位从一个部分乘积到另一个部分乘积的对角线传播，允许同时进行一条线上的所有和; 在最后的14位加法器和中间行的前两个加法器中使用进位选择方法; 使用具有互补通道晶体管逻辑的本发明快速1位全加器。

6. 发明申请

WO1992022924A1 BASIC CELL ARCHITECTURE FOR MASK PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：用于可编程门阵列的基本单元架构
公开(公告)号：WO1992022924A1
公开(公告)日：1992-12-23
申请号：PCT/US1992005003
申请日：1992-06-11
申请人： SIARC
发明人： SIARC , EL GAMAL, Abbas
IPC分类号： H01L27/02
CPC分类号： H01L27/11896 , H01L27/11807 , H03K19/09448 , H03K19/1735
摘要： A highly efficient CMOS cell structure for use in a metal mask programmable gate array, such as a sea-of-gates type gate array, is disclosed herein. In a basic cell, in accordance with one embodiment of the invention, three or more sizes of N-channel transistors (24-35) and three or more sizes of P-channel transistors (18-23 and 36-41) are used. The larger size transistors are incorporated in a drive (12) section of a cell, while the smaller size transistors are incorporated in each compute section (12) of a cell. The particular transistors in the compute and drive sections and the arrangements of the compute and drive sections provide a highly efficient use of silicon real estate while enabling the formation of a wide variety of macrocells to be formed.
摘要翻译：本文公开了一种用于金属掩模可编程门阵列的高效CMOS单元结构，例如海门型门阵列。在基本单元中，根据本发明的一个实施例，使用三个或更多个尺寸的N沟道晶体管（24-35）和三个或更多个尺寸的P沟道晶体管（18-23和36-41）。较大尺寸的晶体管被结合在单元的驱动（12）部分中，而较小尺寸的晶体管被结合在单元的每个计算部分（12）中。计算和驱动部分中的特定晶体管以及计算和驱动部分的布置提供了硅实体的高效利用，同时能够形成要形成的各种宏单元。

7. 发明申请

WO1993017499A1 BI-CMOS OUTPUT CIRCUIT 审中-公开
标题翻译： BI-CMOS输出电路
公开(公告)号：WO1993017499A1
公开(公告)日：1993-09-02
申请号：PCT/JP1990001277
申请日：1990-10-03
申请人： NITTA, Yoshinori , SUGOH, Takeshi , HARA, Hiroyuki
IPC分类号： H03K19/08
CPC分类号： H03K19/09448 , H03K19/001 , H03K19/00353
摘要： A bi-CMOS output circuit composed of a combination of bipolar transistors and a CMOS circuit has a current path of two bipolar transistors connected in series between the power source and ground. When the grounded bipolar transistor is driven by the other bipolar transistor, the output current can be guaranteed when the output voltage is low. When the output voltage is high, however, a large current flows into the bipolar transistor, thereby causing the power source voltage to vary. Therefore, the control input of the grounded bipolar transistor (Q12) is connected to the output terminal of an MOS transistors (M11) through a resistor (R12). In this manner, the grounded bipolar transistor (Q12) is driven by the MOS transistor which has less capability than ordinary bipolar transistors. Therefore, a predetermined current is guaranteed when the output voltage is low, and excessive current is prevented from flowing when the output voltage is high.

8. 发明申请

WO1993017498A1 BiCMOS LOGIC CIRCUIT 审中-公开
标题翻译： BiCMOS逻辑电路
公开(公告)号：WO1993017498A1
公开(公告)日：1993-09-02
申请号：PCT/US1993001894
申请日：1993-02-23
申请人： MICROUNITY SYSTEMS ENGINEERING, INC.
发明人： MICROUNITY SYSTEMS ENGINEERING, INC. , ROSSEEL, Geert , HERNDON, William, H. , MATTHEWS, James, A.
IPC分类号： H03K17/16
CPC分类号： H03K19/086 , H03K17/14 , H03K17/567 , H03K17/603 , H03K19/09448
摘要： An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.
摘要翻译：改进的BiCMOS逻辑电路（70）利用发射极耦合的双极晶体管（21,22）来差分地比较输入信号（Vin）与逻辑参考电平（VBIAS）。每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管（26,27）的网络进行电阻负载。晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号（VREF2）的栅极。控制信号优选地由反馈网络（52,53）提供，反馈网络（52,53）通过温度在网络上保持恒定的电压摆幅。

9. 发明申请

WO1991015060A1 HIGH SPEED LOGIC AND MEMORY FAMILY USING RING SEGMENT BUFFER 审中-公开
标题翻译：高速逻辑和存储器使用环形缓冲器
公开(公告)号：WO1991015060A1
公开(公告)日：1991-10-03
申请号：PCT/US1991001848
申请日：1991-03-20
申请人： THUNDERBIRD TECHNOLOGIES, INC.
发明人： THUNDERBIRD TECHNOLOGIES, INC. , VINAL, Albert, W.
IPC分类号： H03K19/094
CPC分类号： H03K19/01707 , H01L27/0716 , H01L27/11898 , H03K3/03 , H03K3/356156 , H03K17/567 , H03K19/09448 , H03K19/0948
摘要： A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer (20) to couple logic gates (26) to one another in an integrated circuit chip, and to couple memory cells (26) to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer (20) comprises one or more serially connected complementary field effect transistor (FET) inverter stages (21a,..21n), with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET (23a,..23n) in each inverter stage (21a,..21n) has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring Segment Buffer may be replaced by a bipolar transistor-FET driver in which minority carrier lifetime controlled bipolar transistors are used. For logic applications, a Ring Segment Buffer couples each logic gate on a chip to its capacitive load to thereby provide Buffer Cell Logic. Each Ring Segment Buffer is designed to couple the logic gate to its individual capacitive load, while preserving the desired logic chip speed. For memory applications, a memory cell may be coupled to a Ring Segment Buffer which is designed to drive the memory cell's capacitive load at the desired memory chip speed, and also to provide a desired signal delay. Such a Delay Storage cell may be used to design a shift register or binary counter which only requires one clock pulse for operation, because the delay of the Ring Segment Buffer allows internal clocking. The Delay Storage cell may also be used to design a multivibrator, clock generator and other circuits which operate high speed using only one clock pulse. The Buffer Cell Logic and Delay Storage technology of the present invention may operate at speeds of 300 megahertz or more using conventional semiconductor fabrication processes in which conventional CMOS logic and memory technology operates at 70 megahertz or less. A fourfold speed improvement is thereby obtained.

10. 发明申请

WO1990012455A1 BIMOS LEVEL SHIFTER 审中-公开
标题翻译： BIMOS级别更换
公开(公告)号：WO1990012455A1
公开(公告)日：1990-10-18
申请号：PCT/US1990001366
申请日：1990-03-19
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , DAVIS, Darrell, E.
IPC分类号： H03K19/08
CPC分类号： H03K19/017527 , H03K19/09448
摘要： A BIMOS level convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I.C..

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