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    • 1. 发明申请
    • METHOD AND DEVICE FOR SENDING SIGNALS BETWEEN A RADIO FREQUENCY CIRCUIT AND A BASEBAND CIRCUIT
    • 用于在无线电频率电路和基带电路之间发送信号的方法和装置
    • WO2011107587A1
    • 2011-09-09
    • PCT/EP2011/053295
    • 2011-03-04
    • ICERA INCFELIX, Steve
    • FELIX, Steve
    • H04B15/04
    • H04B15/04
    • A method of sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency F C , setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.
    • 一种在设备的射频电路和设备的基带电路之间发送数据信号和时钟信号的方法。 该方法包括:确定数据信号和时钟信号中的至少一个是干扰的,因为它在无线电频带内具有谐波。 如果确定数据信号和时钟信号中的至少一个是干扰的,则该方法还包括:对频率低于时钟频率FC的频率对该至少一个干扰信号进行加扰以使其频谱变平,设置相应的至少一个 指示器,以指示所述至少一个干扰信号已被加扰,以及在所述射频电路和所述基带电路之间发送所述至少一个加扰信号。 该方法还包括在发送所述至少一个加扰信号的步骤之后,如果设置了相应的至少一个指示符,对所述至少一个加扰信号进行解扰。
    • 5. 发明申请
    • ACTIVE POWER MANAGEMENT
    • 有功功率管理
    • WO2010057686A1
    • 2010-05-27
    • PCT/EP2009/056634
    • 2009-05-29
    • ICERA INCCUMMING, PeterHLOND, Marcin
    • CUMMING, PeterHLOND, Marcin
    • G06F1/32
    • G06F1/3203G06F1/324G06F1/3296Y02D10/126Y02D10/172
    • A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application.
    • 一种控制在多个活动期间执行软件的处理器的时钟频率的方法,所述方法包括:对于每个周期:向功率管理应用提供定义具有高频率和低频率的周期的执行简档的至少一个参数 操作间隔; 所述功率管理应用基于所述简档确定用于高频和低频操作间隔的时钟频率; 所述处理器在所述期间的操作周期要求的一段期间内向所述电力管理应用提供; 电源管理应用程序根据操作周期要求确定每个周期的低频间隔的长度; 以及基于由电力管理应用确定的授权时钟频率来控制每个间隔中的时钟频率。
    • 8. 发明申请
    • MEMORY CELLS
    • 记忆细胞
    • WO2009059906A1
    • 2009-05-14
    • PCT/EP2008/064459
    • 2008-10-24
    • ICERA INCMONK KENNETH, Trevor
    • MONK KENNETH, Trevor
    • H01L27/11
    • H01L27/1104G11C11/412H01L27/0207H01L27/11
    • A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.
    • 一种制造集成电路(IC)的方法,包括:限定多个连续有效区域; 形成延伸在有效区域上的导线; 并且使用导线作为掩模,将掺杂剂引入到有源区域中。 在掺杂区域和导线之间提供连接以形成第一和第二电路部分,至少一个有效区域在这些部分之间是连续的。 在该有源区域中,在掺杂区域和导电线之间提供连接以在第一和第二电路部分之间彼此反向偏压地形成一对二极管连接的晶体管,这些晶体管连接成在第一和第二电路部分之间留下共用的未连接的掺杂区域 对。 本发明还涉及相应的IC。
    • 10. 发明申请
    • DETECTING EXCESS CURRENT LEAKAGE OF A CMOS DEVICE
    • 检测CMOS器件的过电流泄漏
    • WO2006090125A3
    • 2007-01-18
    • PCT/GB2006000569
    • 2006-02-17
    • ICERA INCHUGHES PETER WILLIAM
    • HUGHES PETER WILLIAM
    • H03K17/16G01R31/26
    • H03K17/165
    • A system (10, 90) , apparatus (12, 30, 40, 50, 60, 70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36, 46) within a complementary MOS (CMOS) environment. A load control (32, 42) is arranged as a compliment to the MOS transistor. A comparator (34, 44) is electrically connected to the load control and the MOS transistor, and produces an output signal representative of the detection of a current leakage exceeding a threshold. In response to the received output signal indicating an excess current leakage, system voltage/frequency may be adjusted to prevent damage to the CMOS environment .
    • 公开了一种用于检测金属氧化物半导体(MOS)晶体管(36)的漏极/源极之间的过剩电流泄漏的系统(10,90),装置(12,30,40,50,60,70)和方法(100) 46)在互补MOS(CMOS)环境中。 负载控制(32,42)被配置为对MOS晶体管的补充。 比较器(34,44)电连接到负载控制和MOS晶体管,并且产生表示超过阈值的电流泄漏检测的输出信号。 响应于接收的输出信号指示过大的电流泄漏,可以调节系统电压/频率以防止损坏CMOS环境。