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1. 发明申请

WO1995006979A1 LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY 审中-公开
标题翻译：逻辑结构和电路快速携带
公开(公告)号：WO1995006979A1
公开(公告)日：1995-03-09
申请号：PCT/US1994009864
申请日：1994-08-31
申请人： XILINX, INC.
发明人： XILINX, INC. , NEW, Bernard, J.
IPC分类号： H03K19/177
CPC分类号： G06F7/503 , G06F2207/4812 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17732
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.
摘要翻译：使用包括多个组合函数发生器和存储元件块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。本发明利用以下事实：当要添加的两个二进制位不相等时，要添加到两个位的进位信号可以传播到下一个更高有效位，并且该位中的一个可以用作进位信号，当这些位是相等的。对于每个位，进位传播信号由查找表可编程函数发生器产生，并被专用硬件用于生成进位信号。

2. 发明申请

WO1998051013A1 METHOD AND STRUCTURE FOR PROVIDING FAST CONDITIONAL SUM IN A FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：在现场可编程门阵列中提供快速条件的方法和结构
公开(公告)号：WO1998051013A1
公开(公告)日：1998-11-12
申请号：PCT/US1997015368
申请日：1997-08-28
申请人： XILINX, INC.
发明人： XILINX, INC. , NEW, Bernard, J.
IPC分类号： H03K19/173
CPC分类号： G06F7/507 , G06F7/503 , G06F2207/4812 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.
摘要翻译：用于现场可编程门阵列（FPGA）的进位逻辑电路，其允许进位输入信号通过进位逻辑电路传播而不通过另一串联电路元件的多路复用器。进位逻辑电路使用FPGA的函数发生器来响应于提供给进位逻辑电路的第一和第二输入信号来提供传播信号。还描述了在FPGA中执行进位逻辑功能的方法。

3. 发明申请

WO1993008523A2 1-BIT ADDER AND MULTIPLIER CONTAINING A 1-BIT ADDER 审中-公开
标题翻译：包含1位加法器的1位加法器和乘法器
公开(公告)号：WO1993008523A2
公开(公告)日：1993-04-29
申请号：PCT/EP1992002350
申请日：1992-10-12
申请人： THOMSON CONSUMER ELECTRONICS S.A. , CHAN YAN FONG, Joseph
发明人： THOMSON CONSUMER ELECTRONICS S.A.
IPC分类号： G06F07/50
CPC分类号： G06F7/5338 , G06F7/501 , G06F7/507 , G06F2207/3884 , G06F2207/4812 , G06F2207/4816 , H03K19/09448
摘要： E.g. for video applications fast multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough. The inventive multiplier in nearly full CMOS design has been constructed with a 1.2 mu BICMOS technology, having a multiplication time of 9 ns with a supply voltage of 5 volts. Minimum multiplication time has been achieved by a combination of the following techniques: use of the Booth-Mc Sorley algorithm in order to reduce the number of partial products; diagonal propagation of the carry from one partial product to the other allowing all the sums on one line to be done simultaneously; use of the carry select approach in the final 14 bits adder and in the first two adders in the intermediate rows; use of inventive fast one-bit full adders with complementary pass transistor logic.
摘要翻译：例如。对于视频应用，需要具有高分辨率的快速乘法器。但是更高的分辨率导致更多的部分产品被内部计算。可以使用Booth-Mc Sorley算法来减少所需数量的这种部分产品。该算法可以与进位从一个部分乘积到另一个的对角线传播组合，允许同时计算一条线上的所有和。但可达乘法时间不够短。几乎全CMOS设计中的创造性乘法器已经用1.2微米的BICMOS技术构建，具有9ns的乘法时间，电源电压为5伏。通过以下技术的组合实现了最小乘法时间：使用Booth-Mc Sorley算法来减少部分乘积; 进位从一个部分乘积到另一个部分乘积的对角线传播，允许同时进行一条线上的所有和; 在最后的14位加法器和中间行的前两个加法器中使用进位选择方法; 使用具有互补通道晶体管逻辑的本发明快速1位全加器。

4. 发明申请

WO00034853A1 A SERIAL-PARALLEL BINARY MULTIPLIER 审中-公开
标题翻译：串并行二进制乘法器
公开(公告)号：WO00034853A1
公开(公告)日：2000-06-15
申请号：PCT/GB1999/003897
申请日：1999-11-24
IPC分类号： G06F7/52
CPC分类号： G06F7/5272 , G06F7/5332 , G06F7/5334 , G06F2207/4812
摘要： A serial binary multiplier multiplies two operands to provide a product. A first operand is stored locally and a second operand is transmitted serially whilst simultaneously multiplying said first operand with all possible values of said second operand taking into account any received bits of the second operand. All possible results are added to the contents of a partial result register and stored and when a complete element of the full second operand has been received and decoded, the correct result is selected by the decoder. The new partial product is shifted in the register and when all the bits of the second operand have been received the final product is output to a serial to parallel converter. The method and circuit permit part of the multiplication process to be performed whilst the input data is still being transmitted thereby reducing the operation delay. In a 1-bit two's complement embodiment a decoder is used to decide whether to add or substract the received bit of the serially transmitted operand to or from the contents of the partial result register. The decoder uses knowledge of the previously transmitted bit of the operand to make this decision.
摘要翻译：串行二进制乘法器将两个操作数相乘以提供产品。第一操作数被本地存储，并且第二操作数被串行发送，同时将所述第一操作数与所述第二操作数的所有可能值相乘，同时考虑到第二操作数的任何接收位。所有可能的结果被添加到部分结果寄存器的内容中并存储，并且当完整的第二操作数的完整元素已被接收和解码时，解码器选择正确的结果。新的部分产品在寄存器中移位，当第二个操作数的所有位都被接收到时，最终产品被输出到串行到并行转换器。方法和电路允许在输入数据仍然被传输的同时执行乘法处理的一部分，从而减少操作延迟。在1比特二进制补码实施例中，解码器用于决定是否将部分结果寄存器的内容的串行发送操作数的接收比特加或减。解码器使用操作数的先前发送的位的知识来做出该决定。

5. 发明申请

WO1991000568A1 CONDITIONAL-SUM CARRY STRUCTURE COMPILER 审中-公开
标题翻译：条件式结构编译器
公开(公告)号：WO1991000568A1
公开(公告)日：1991-01-10
申请号：PCT/US1990003461
申请日：1990-06-22
申请人： VLSI TECHNOLOGY, INC.
发明人： VLSI TECHNOLOGY, INC. , ASATO, Creighton, Satoshi , DITZEN, Christoph
IPC分类号： G06F07/50
CPC分类号： G06F7/507 , G06F17/5045 , G06F2207/4812
摘要： A conditional-sum carry structure (11) has architecture which is sufficiently regular that the structure can be conveniently generated by automated compiler. The carry structure (11) includes a column of input cells (left column), each of the cells (CC) in the column being operative for receiving binary numbers (A, B) and, for each of the received numbers, generating a sum bit (S) and two carry-out bits (C0, C1). Further the carry structure (11) includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplixer and exclusive OR gate circuits (MUX XOR elements) and multiplixer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure (11).

6. 发明申请

WO1990002994A1 CIRCUITS FOR ADDING OR SUBTRACTING BCD-CODED OR DUAL-CODED OPERANDS 审中-公开
标题翻译：用于增加或减少BCD编码或双码操作的电路
公开(公告)号：WO1990002994A1
公开(公告)日：1990-03-22
申请号：PCT/DE1989000569
申请日：1989-08-31
申请人： SIEMENS AKTIENGESELLSCHAFT , FISCHER, Horst , ROHSAINT, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/50
CPC分类号： G06F7/494 , G06F2207/4812 , G06F2207/4921
摘要： A circuit is disclosed which allows BCD-coded or dual-coded operands to be added or subtracted with a single dual-adder. To allow BCD linkages to be made, the BCD operands are entered into the dual adder (DAA) through input stages (EG1, EG2). The first input stage (EG1) reverses the associated operand (A) when this operand has a negative sign. The other input stage (EG2) prepares the associated operand (B) in such a way that the number 6 is added to the associated operand (B) in the case of positive operands (A, B), and in the case of negative operands (A, B) the number 6 is added to the associated operand (B) and the result is reversed. In the case of dual-coded operands, the associated operands are reversed when they have a negative sign, otherwise they remain unchanged. After the prepared operands (X, Y) are linked in the dual adder (DA), a correction of the sum result (S) might be required in the case of BCD-linkages. This is what happens when a carry-signal (C) appears at the highest position of the sum result in the case of a dual linkage in the dual adder (DA). In this case, the number 6 is subtracted from the sum result (S) in an output stage (AGS), thus giving a corrected sum (R). This circuit allows BCD numbers and dual numbers to be added and subtracted with a single dual adder.
摘要翻译：公开了一种电路，其允许用单个双加法器来添加或减去BCD编码或双重编码的操作数。为了允许BCD连接，BCD操作数通过输入级（EG1，EG2）输入到双加法器（DAA）中。当该操作数具有负号时，第一个输入级（EG1）反转相关的操作数（A）。另一个输入级（EG2）在正操作数（A，B）的情况下，以相对应的操作数（B）的方式将编号6加到相关的操作数（B），并在负操作数（A，B）将6号添加到相关联的操作数（B），结果相反。在双重编码操作数的情况下，相关的操作数在它们具有负号时相反，否则它们保持不变。在双加法器（DA）中连接准备的操作数（X，Y）之后，在BCD连接的情况下可能需要求和（S）的校正。当在双加法器（DA）中双重连接的情况下，在结果的最高位置出现进位信号（C）时，会发生什么。在这种情况下，从输出级（AGS）中的和结果（S）中减去数字6，从而给出校正的和（R）。该电路允许使用单个双加法器来添加和减去BCD号和双数。

7. 发明申请

WO1985005705A1 AN XxY BIT ARRAY MULTIPLIER/ACCUMULATOR CIRCUIT 审中-公开
标题翻译：一个XxY位阵列乘法器/累加器电路
公开(公告)号：WO1985005705A1
公开(公告)日：1985-12-19
申请号：PCT/US1985000511
申请日：1985-03-28
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , KLOKER, Kevin, L. , CIESLAK, Ronald, H.
IPC分类号： G06F07/52
CPC分类号： G06F7/533 , G06F7/4991 , G06F7/49994 , G06F7/5016 , G06F7/5332 , G06F7/5443 , G06F2207/3876 , G06F2207/4812
摘要： An XxY bit array multiplier/accumulator circuit (10), where X and Y are integers, for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders (13) and multiplexers (12) in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry (14) and signed/unsigned modes of operation (15) are provided.

8. 发明申请

WO2018063656A3 INTEGRATED CIRCUITS WITH SPECIALIZED PROCESSING BLOCKS FOR PERFORMING FLOATING-POINT FAST FOURIER TRANSFORMS AND COMPLEX MULTIPLICATION 审中-公开
公开(公告)号：WO2018063656A3
公开(公告)日：2018-07-12
申请号：PCT/US2017049015
申请日：2017-08-29
申请人： ALTERA CORP
发明人： LANGHAMMER MARTIN
IPC分类号： H03K19/177 , G06F7/42 , G06F7/44
CPC分类号： G06F7/483 , G06F7/4812 , G06F7/5443 , G06F17/142 , G06F2207/4812
摘要： Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.

9. 发明申请

WO9308523A3 1-BIT ADDER AND MULTIPLIER CONTAINING A 1-BIT ADDER 审中-公开
标题翻译：包含1位加法器的1位加法器和乘法器
公开(公告)号：WO9308523A3
公开(公告)日：1993-05-27
申请号：PCT/EP9202350
申请日：1992-10-12
申请人： THOMSON CONSUMER ELECTRONICS
发明人： CHAN YAN FONG JOSEPH
IPC分类号： G06F7/507 , G06F7/50 , G06F7/52 , G06F7/527 , G06F7/53 , G06F7/533 , H03K19/0944
CPC分类号： G06F7/5338 , G06F7/501 , G06F7/507 , G06F2207/3884 , G06F2207/4812 , G06F2207/4816 , H03K19/09448
摘要： E.g. for video applications fast multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough. The inventive multiplier in nearly full CMOS design has been constructed with a 1.2 ν BICMOS technology, having a multiplication time of 9 ns with a supply voltage of 5 volts. Minimum multiplication time has been achieved by a combination of the following techniques: use of the Booth-Mc Sorley algorithm in order to reduce the number of partial products; diagonal propagation of the carry from one partial product to the other allowing all the sums on one line to be done simultaneously; use of the carry select approach in the final 14 bits adder and in the first two adders in the intermediate rows; use of inventive fast one-bit full adders with complementary pass transistor logic.

10. 发明申请

WO1986007173A1 CMOS FULL ADDER CELL E.G. FOR MULTIPLIER ARRAY 审中-公开
标题翻译： CMOS FULL ADDER CELL E.G. 多用户阵列
公开(公告)号：WO1986007173A1
公开(公告)日：1986-12-04
申请号：PCT/US1986000250
申请日：1986-02-04
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , ADAIR, Robert, L.
IPC分类号： G06F07/50
CPC分类号： G06F7/501 , G06F2207/4812 , G06F2207/4816 , H03K19/0948 , H03K19/215
摘要： A fast full adder cell, for use in multiplier arrays. The cell uses simple 2-input gates (16, 18, 22, 24) and a pair of multiplexers (11, 21) made from pass transistors (12, 14, 26, 28). The 2-input gates (16, 18, 22, 24) may also be made from pass transistors and, in the case of AND and OR gates, a single additional field-effect transistor. In a first embodiment, the cell employs a one-bit-wide multiplexer (11) for selecting as the sum output either the output of a 2-input exclusive-OR gate (16) or the output of a 2-input exclusive-NOR gate (18). A second one-bit-wide multiplexer (21) selects as the cell's carry output either the output of a 2-input OR gate (24) or the output of a 2-input AND gate (22). In a second embodiment, the 2-input exclusive-OR and exclusive-NOR gates also are formed from either one or two single-bit multiplexers (Figs. 3 and 4, respectively), while the AND and OR gates are formed from pass transistors (36, 42) with a pull-up or pull-down transistor (38, 44) on their outputs, as appropriates. Both the P-type device and the N-type device of each pass transistor are formed with the same minimum possible with; to compensate for unequal propagation of 1's and 0's, an inverter follows each pair of pass transistors and the P-type and N-type devices of the inverter are of approximately the same size.
摘要翻译：一个快速全加器单元，用于乘法器阵列。单元使用由传输晶体管（12,14,26,28）制成的简单的2输入栅极（16,18,22,24）和一对多路复用器（11,21）。 2输入栅极（16,18,22,24）也可以由传输晶体管制成，并且在AND和OR门的情况下，单个附加的场效应晶体管。在第一实施例中，单元采用一位宽多路复用器（11），用于选择输出2-输入异或门（16）的输出或2-输入异或（NOR-NOR）的输出门（18）。第二个一比特多路复用器（21）选择2输入或门（24）的输出或2输入与门（22）的输出作为单元的进位输出。在第二实施例中，2输入异或异或异或门也由一个或两个单比特多路复用器（分别为图3和4）形成，而AND和OR门由传输晶体管（36,42），在其输出上具有上拉或下拉晶体管（38,44），作为适当的。每个通过晶体管的P型器件和N型器件均以相同的最小值形成; 为了补偿1和0的不均匀传播，逆变器遵循每对传输晶体管，并且逆变器的P型和N型器件的尺寸大致相同。

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