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1. 发明申请

WO2004065934A2 SEMICONDUCTOR FABRICATION METHOD FOR MAKING SMALL FEATURES 审中-公开
标题翻译：制造小功能的半导体制造方法
公开(公告)号：WO2004065934A2
公开(公告)日：2004-08-05
申请号：PCT/US2004/001219
申请日：2004-01-16
申请人： MOTOROLA INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： G01N
CPC分类号： H01L21/3085 , H01L21/3083 , H01L21/31144 , Y10S438/947 , Y10S438/976 , Y10S438/978
摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N 2 plasma.
摘要翻译：一种半导体制造方法，包括在半导体衬底（102）上形成包括成像层（112）和下层（110）的膜（109）。成像层（112）被图案化以产生具有印刷尺寸（124）的印刷特征（116）。然后，下层（110）被处理以在下层（110）中产生倾斜的侧壁空隙（120），其中空隙（120）具有接近底层基底的成品尺寸（126），小于印刷尺寸。处理底层（110）可以包括将晶片暴露于高密度低压N2等离子体。

2. 发明申请

WO99027571A1 UNLANDED VIA STRUCTURE AND METHOD FOR MAKING SAME 审中-公开
标题翻译：通过其制造方法的结构和方法
公开(公告)号：WO99027571A1
公开(公告)日：1999-06-03
申请号：PCT/US1998/008617
申请日：1998-04-29
IPC分类号： H01L21/768 , H01L23/522 , H01L21/302
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76877 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material (212) using substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric, and then concurrently stripping the photoresist, and anisotropically etching the organic polymer intra-layer dielectric. A second conductor (218) is typically deposited into the via opening so as to form an electrical connection to the first conductor (206). A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.
摘要翻译：用于微电子器件的高密度，低电容互连结构具有使用基本垂直侧壁的有机聚合物内层介电材料（212）形成的无空隙通孔。一种制造无衬底通孔的方法包括在导体之间形成平面化的有机聚合物层内电介质，在导体和有机聚合物层上形成无机电介质，图案化光致抗蚀剂层，使得光致抗蚀剂层中的开口与导体和层内电介质，蚀刻无机电介质，然后同时剥离光致抗蚀剂，并各向异性蚀刻有机聚合物层内电介质。通常将第二导体（218）沉积到通孔开口中，以形成与第一导体（206）的电连接。也可以使用包含有机聚合物的硅基绝缘体来形成层间电介质。

3. 发明申请

WO1996004680A1 METHOD OF REMOVING SHARP EDGES OF DIELECTRIC COATINGS ON SEMICONDUCTOR SUBSTRATES AND DEVICE PRODUCED 审中-公开
标题翻译：在半导体衬底上去除电介质涂层的夏普片的方法和生产的器件
公开(公告)号：WO1996004680A1
公开(公告)日：1996-02-15
申请号：PCT/US1995009968
申请日：1995-07-21
申请人： MICROCHIP TECHNOLOGY, INC.
发明人： MICROCHIP TECHNOLOGY, INC. , JACKSON, Daniel, J.
IPC分类号： H01L21/44
CPC分类号： H01L21/76819 , Y10S438/978
摘要： This disclosure is directed to a method of producing a smooth surface for a dielectric coating (34) that is located above the surface of semiconductor substrate (10) containing doped regions (26, 32, 34) of a semiconductor device. Sharp edges (40, 42) formed in the dielectric coating (34) during certain semiconductor processing steps are removed using a deposition process to deposit a separate insulating layer (48) on the dielectric coating (34) containing the sharp edges (40, 42) followed by an annealing operation and the subsequent removal of the separate insulating layer (48) to permit the subsequent formation of electrodes (50, 52, 54) on a smooth surface of the dielectric coating (34).
摘要翻译：本公开涉及一种制造用于介电涂层（34）的平滑表面的方法，所述介电涂层位于包含半导体器件的掺杂区域（26,32,34）的半导体衬底（10）的表面上方。在某些半导体处理步骤中形成在电介质涂层（34）中的尖锐边缘（40,42）使用沉积工艺去除，以在包含尖锐边缘（40,42）的电介质涂层（34）上沉积单独的绝缘层（48）），然后进行退火操作，随后移除单独的绝缘层（48）以允许随后在电介质涂层（34）的光滑表面上形成电极（50,52,54）。

4. 发明申请

WO1992006394A1 SELF-ALIGNED V-GROOVES AND WAVEGUIDES 审中-公开
标题翻译：自对准V-GROOVES和WAVEGUIDES
公开(公告)号：WO1992006394A1
公开(公告)日：1992-04-16
申请号：PCT/GB1991001699
申请日：1991-10-02
申请人： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY , WELBOURN, Anthony, David
发明人： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
IPC分类号： G02B06/12
CPC分类号： G02B6/136 , Y10S438/978
摘要： A method of forming a pair of V-grooves in alignment with an array of planar waveguides comprises the steps of simultaneously forming cores (5) for the waveguides and windows (6) for the V-grooves (8), covering the cores with a protective layer (7), and forming the V-grooves through the windows. The method is such that the V-grooves (8) are formed on each side of the array of waveguides.
摘要翻译：形成与平面波导阵列对准的一对V形槽的方法包括以下步骤：同时形成用于V形槽（8）的波导和窗口（6）的芯（5），用一个保护层（7），并通过窗户形成V形槽。该方法使得V形槽（8）形成在波导阵列的每一侧上。

5. 发明申请

WO1988002187A1 SEMICONDUCTOR STRUCTURES AND A METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：半导体结构和制造半导体结构的方法
公开(公告)号：WO1988002187A1
公开(公告)日：1988-03-24
申请号：PCT/GB1987000667
申请日：1987-09-22
申请人： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY , COOPER, David, Martin , NELSON, Andrew, William , COLE, Simon , LEALMAN, Ian, Francis , DEVLIN, William, John
发明人： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
IPC分类号： H01L33/00
CPC分类号： H01L33/24 , H01L21/30612 , H01L33/0062 , H01S5/2201 , H01S5/227 , H01S5/2275 , H01S5/32391 , Y10S438/978
摘要： In a semiconductor buried heterostructure laser, having a mesa (2, 3, 4) and confinement layers (5, 6, 7) on a substrate (12), at least the lowermost of the confinement layers (5, 6, 7) is substantially planar up to the mesa. This is achieved by MOVPE growth of InP against lateral surfaces of the mesa (2, 3, 4) which are defined by distinct crystallographic planes of the material of the mesa. In particular (111) B InP planes are used. The laser is particularly for use in the field of optical communications.

6. 发明申请

WO2010088183A1 STRUCTURE AND METHOD FOR FABRICATING CLADDED CONDUCTIVE LINES IN MAGNETIC MEMORIES 审中-公开
标题翻译：用于在磁记忆体中制造层状导电线的结构和方法
公开(公告)号：WO2010088183A1
公开(公告)日：2010-08-05
申请号：PCT/US2010/021979
申请日：2010-01-25
申请人： EVERSPIN TECHNOLOGIES, INC. , SMITH, Kenneth H. , RIZZO, Nicholas D. , AGGARWAL, Sanjeev , CIANCIO, Anthony , BUTCHER, Biran R.
发明人： SMITH, Kenneth H. , RIZZO, Nicholas D. , AGGARWAL, Sanjeev , CIANCIO, Anthony , BUTCHER, Biran R.
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1659 , H01L23/53238 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： A method of forming a magnetoelectronic device includes forming a dielectric material surrounding a magnetic bit, etching the dielectric material defining an opening over the magnetic bit without exposing the magnetic bit, the opening having a sidewall, depositing a blanket layer of cladding material over the dielectric material, including over the sidewall, removing by a sputtering process the blanket layer in the bottom of the opening and the dielectric mateπal over the magnetic bit, and forming a conductive mateπal within the opening to form a bit line. This process reduces errors caused by process irregularities such as edges of the bits protruding and thereby causing defects in the cladding layer formed thereover. A bit line or digit line so formed may optionally be tapered at the ends to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.
摘要翻译：一种形成磁电子器件的方法包括形成围绕磁头的电介质材料，蚀刻在磁性钻头上限定开口的电介质材料，而不暴露磁性钻头，该开口具有侧壁，在电介质上沉积包层材料的覆盖层材料，包括在侧壁上，通过溅射工艺去除开口底部的覆盖层和在磁头上的介电材料，并在开口内形成导电材料以形成位线。该处理减少由诸如突起的边缘的处理不规则性引起的错误，从而在其上形成的包层中引起缺陷。如此形成的位线或数字线可以可选地在端部是锥形的，以防止由于外部磁场而可能发生的位线磁矩的磁性反转。

7. 发明申请

WO2006047116A1 NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION 审中-公开
标题翻译：具有较薄体部分的非平面装置和制造方法
公开(公告)号：WO2006047116A1
公开(公告)日：2006-05-04
申请号：PCT/US2005/037169
申请日：2005-10-13
申请人： INTEL CORPORATION , SHAH, Uday , DOYLE, Brian , BRASK, Justin , CHAU, Robert , LETSON, Thomas
发明人： SHAH, Uday , DOYLE, Brian , BRASK, Justin , CHAU, Robert , LETSON, Thomas
IPC分类号： H01L29/786 , H01L21/336 , H01L29/423
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中顶表面处的横向相对侧壁之间的距离大于底表面处的距离。栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

8. 发明申请

WO1993009558A1 SELF-ALIGNED GATED ELECTRON FIELD EMITTER 审中-公开
标题翻译：自对准栅电子场发射器
公开(公告)号：WO1993009558A1
公开(公告)日：1993-05-13
申请号：PCT/US1992007488
申请日：1992-09-04
申请人： BELL COMMUNICATIONS RESEARCH, INC.
发明人： BELL COMMUNICATIONS RESEARCH, INC. , BAGLEY, Brian, G. , MARCUS, Robert, Boris , RAVI, Tirunelveli, Subramaniam
IPC分类号： H01J09/04
CPC分类号： H01J3/022 , H01J9/025 , Y10S438/978
摘要： A method of fabricating a self-aligned gated electron field emitter. An oxidation process forms an optimized, atomically sharp needle (18) in a silicon substrate (12). The needle and surrounding planar area is conformally coated with silicon dioxide (22). A dielectric layer (24) is deposited and planarized over the needle. The dielectric layer is partially etched away to expose the coated needle. The exposed silicon dioxide needle is isotropically etched so as to undercut the dielectric layer. A gate metal is directionally deposited so as to form a gate layer (26) on the planar portions of the dielectric layer that is electrically isolated from the gate metal (28) deposited on the needle. The metal on the needle is anodically etched by applying the potential only to the silicon and not to the gate layer. Electro-plating may recoat the needle with another metal (30). The silicon substrate may be replaced by a glass substrate (42) on which is deposited a polysilicon or amorphous silicon layer (40).

9. 发明申请

WO1985004049A1 IMPROVED INTEGRATED CIRCUIT STRUCTURE HAVING INTERMEDIATE METAL SILICIDE LAYER AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有中间金属硅化物层的改进的集成电路结构及其制造方法
公开(公告)号：WO1985004049A1
公开(公告)日：1985-09-12
申请号：PCT/US1985000307
申请日：1985-02-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , CHEUNG, Robin, W. , CHAN, Hugo, W., K.
IPC分类号： H01L29/04
CPC分类号： H01L21/76889 , H01L21/76801 , H01L21/76834 , H01L21/76895 , H01L23/53271 , H01L29/41725 , H01L29/4933 , H01L2924/0002 , Y10S148/019 , Y10S148/133 , Y10S148/147 , Y10S257/904 , Y10S438/978 , H01L2924/00
摘要： An improved integrated circuit structure characterized by enhanced step coverage and a method of making it. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon (10) having selected portions thereof reacted with a metal capable of forming a metal silicide (60) in situ on the surface of the poly silicon strips, a further oxide layer (62) over the metal silicide, and a metal layer (65) providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer (50a) above the poly load resistor (10d). This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers (58) via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure .

10. 发明申请

WO2004065934A8 SEMICONDUCTOR FABRICATION METHOD FOR MAKING SMALL FEATURES 审中-公开
标题翻译：制造小功能的半导体制造方法
公开(公告)号：WO2004065934A8
公开(公告)日：2005-08-04
申请号：PCT/US2004001219
申请日：2004-01-16
申请人： FREESCALE SEMICONDUCTOR INC , SPARKS TERRY G , SINGHAL AJAY , STROZEWSKI KIRK J
发明人： SPARKS TERRY G , SINGHAL AJAY , STROZEWSKI KIRK J
IPC分类号： G01N20060101 , G03F7/00 , G03F7/36 , H01L21/027 , H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L21/3085 , H01L21/3083 , H01L21/31144 , Y10S438/947 , Y10S438/976 , Y10S438/978
摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.
摘要翻译：一种半导体制造方法，包括在半导体衬底（102）上形成包括成像层（112）和下层（110）的膜（109）。成像层（112）被图案化以产生具有印刷尺寸（124）的印刷特征（116）。然后，下层（110）被处理以在下层（110）中产生倾斜的侧壁空隙（120），其中空隙（120）具有接近底层基底的成品尺寸（126），小于印刷尺寸。处理底层（110）可以包括将晶片暴露于高密度低压N2等离子体。

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