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1. 发明申请

WO2004065287A2 A METHOD OF PATTERNING PHOTORESIST ON A WAFER USING A TRANSMISSION MASK WITH A CARBON LAYER 审中-公开
标题翻译：使用传输掩模与碳层在波形上绘制光刻胶的方法
公开(公告)号：WO2004065287A2
公开(公告)日：2004-08-05
申请号：PCT/US2004/001226
申请日：2004-01-16
申请人： MOTOROLA INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： B81B
CPC分类号： G03F1/74 , G03F1/50 , G03F1/58 , G03F1/72
摘要： A photoresist layer (417) on a semiconductor wafer (419) is patterned using a mask (401) with an absorbing layer (107) that has been repaired by using an additional light-absorbing carbon layer (105) that collects ions that are used in the repair process. After the repair has been completed, the ions that are present in the carbon layer (105) are removed by removing the portion of the carbon layer (105) that is not covered by the absorbing layer (107). Thus, the absorbing layer (107), which contains the pattern that is to be exposed on the photoresist layer (417), also acts as a mask in the removal of the portion of the carbon layer (105) that contains the ions. Thereby the ions that are opaque at the particular wavelength being used are removed from the areas where light is intended to pass through the mask to the photoresist (417). The buffer (105) layer is made absorbing to avoid problems with reflections at interfaces thereof.
摘要翻译：使用具有吸收层（107）的掩模（401）对半导体晶片（419）上的光致抗蚀剂层（417）进行图案化，该吸收层已经通过使用收集所使用的离子的附加光吸收碳层（105）进行修复在维修过程中。在完成修复之后，通过除去未被吸收层（107）覆盖的碳层（105）的部分来除去存在于碳层（105）中的离子。因此，含有要在光致抗蚀剂层（417）上露出的图案的吸收层（107）也用作除去含有离子的碳层（105）的部分的掩模。因此，在所要使用的特定波长处不透明的离子从光通过掩模的区域去除到光致抗蚀剂（417）。吸收缓冲层（105）以避免其界面处的反射问题。

2. 发明申请

WO2004065934A2 SEMICONDUCTOR FABRICATION METHOD FOR MAKING SMALL FEATURES 审中-公开
标题翻译：制造小功能的半导体制造方法
公开(公告)号：WO2004065934A2
公开(公告)日：2004-08-05
申请号：PCT/US2004/001219
申请日：2004-01-16
申请人： MOTOROLA INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： G01N
CPC分类号： H01L21/3085 , H01L21/3083 , H01L21/31144 , Y10S438/947 , Y10S438/976 , Y10S438/978
摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N 2 plasma.
摘要翻译：一种半导体制造方法，包括在半导体衬底（102）上形成包括成像层（112）和下层（110）的膜（109）。成像层（112）被图案化以产生具有印刷尺寸（124）的印刷特征（116）。然后，下层（110）被处理以在下层（110）中产生倾斜的侧壁空隙（120），其中空隙（120）具有接近底层基底的成品尺寸（126），小于印刷尺寸。处理底层（110）可以包括将晶片暴露于高密度低压N2等离子体。

3. 发明申请

WO2004079779A2 A METHOD OF PATTERNING PHOTORESIST ON A WAFER USING AN ATTENUATED PHASE SHIFT MASK 审中-公开
标题翻译：使用衰减相移片掩模在波形上绘制光电子的方法
公开(公告)号：WO2004079779A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/004327
申请日：2004-02-13
申请人： FREESCALE SEMICONDUCTOR, INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： H01L
CPC分类号： G03F1/32
摘要： An attenuated phase shift mask (10 or 20) includes a substrate (12 or 22) and an attenuation stack (11 or 21) overlying the substrate. The attenuation stack includes a chromium layer or ruthenium layer (14 or 24) overlying the substrate, a tantalum silicon oxide layer (16 or 26) overlying the chromium layer or the ruthenium layer, and a tantalum silicon nitride layer (18 or 28) overlying the tantalum silicon oxide layer. The attenuation stack may also include a layer (30) between the substrate (22) and the chromium or ruthenium layer (24). In one embodiment, this layer is a portion of the substrate. The attenuation stack is used to pattern photoresist (50) on a semiconductor wafer. In one embodiment, portions of the substrate adjacent the attenuation stack has a transmission of greater than 90 percent and the attenuation stack has a transmission of 5 to 20 percent at the exposure wavelength. In one embodiment, an inspection contrast between the substrate and the attenuation stack at an inspection wavelength is greater than 75 percent.
摘要翻译：衰减的相移掩模（10或20）包括衬底（12或22）和覆盖衬底的衰减叠层（11或21）。衰减堆叠包括覆盖在衬底上的铬层或钌层（14或24），覆盖在铬层或钌层上的钽氧化硅层（16或26）以及叠置在其上的钽氮化硅层（18或28）钽氧化硅层。衰减堆叠还可以包括在基底（22）和铬或钌层（24）之间的层（30）。在一个实施例中，该层是衬底的一部分。衰减堆叠用于在半导体晶片上图案化光致抗蚀剂（50）。在一个实施例中，与衰减堆叠相邻的衬底的部分具有大于90％的透射率，并且衰减堆叠在曝光波长处具有5至20％的透射率。在一个实施例中，在检查波长处的衬底和衰减叠层之间的检查对比度大于75％。

4. 发明申请

WO2004079780A2 A METHOD OF PATTERNING PHOTORESIST ON A WAFER USING A REFLECTIVE MASK WITH A MULTI-LAYER ARC 审中-公开
标题翻译：使用具有多层ARC的反射掩模在波形上绘制光刻胶的方法
公开(公告)号：WO2004079780A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/004328
申请日：2004-02-13
申请人： FREESCALE SEMICONDUCTOR, INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： H01L
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/46 , G03F1/54
摘要： A patterned reflective semiconductor mask (10) uses a multiple layer ARC (24, 26, 28) overlying an absorber stack (22) that overlies a reflective substrate (12, 14). The absorber stack has more than one layer and an upper layer of the absorber stack has a predetermined metal. The multiple layer ARC overlying the upper layer of the absorber stack has layers of nitrogen, oxygen and nitrogen combined with the predetermined metal of the upper layer of the absorber stack. The oxygen layer in the ARC has less metallic properties than the nitrogen layers therein. In one form, an overlying dielectric layer (30) is positioned on the multiple layer ARC to increase light interference. The ARC provides wide bandwidth inspection contrast for extreme ultra-violet (EUV) reticles.
摘要翻译：图案化反射半导体掩模（10）使用覆盖在反射基板（12,14）上的吸收体堆叠（22）上的多层ARC（24,26,28）。吸收体堆叠具有多于一层，吸收体层的上层具有预定的金属。覆盖吸收体堆叠的上层的多层ARC具有与吸收体堆叠的上层的预定金属组合的氮，氧和氮层。 ARC中的氧层具有比其中的氮层少的金属性质。在一种形式中，覆盖介质层（30）位于多层ARC上以增加光干涉。 ARC为极紫外（EUV）光罩提供宽带宽检测对比度。

5. 发明申请

WO2004065934A3 SEMICONDUCTOR FABRICATION METHOD FOR MAKING SMALL FEATURES 审中-公开
公开(公告)号：WO2004065934A3
公开(公告)日：2004-08-05
申请号：PCT/US2004/001219
申请日：2004-01-16
申请人： FREESCALE SEMICONDUCTOR, INC. , WASSON, James, R. , MANGAT, Pawitter
发明人： WASSON, James, R. , MANGAT, Pawitter
IPC分类号： G03F7/00
摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N 2 plasma.

6. 发明申请

WO2004076051A2 REACTOR CLAMP 审中-公开
标题翻译：反应器夹
公开(公告)号：WO2004076051A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/000165
申请日：2004-01-07
申请人： ARGONAUT TECHNOLOGIES, INC. , MEIER, Daniel, J. , WASSON, James, R.
发明人： MEIER, Daniel, J. , WASSON, James, R.
IPC分类号： B01J
CPC分类号： B01L3/565 , B01J3/03 , B01J19/004 , B01J19/0046 , B01J2219/00011 , B01J2219/00065 , B01J2219/002 , B01J2219/00213 , B01J2219/0024 , B01J2219/0027 , B01J2219/00698 , B01L9/50
摘要： A modular reactor system (10) comprises a backplane (12) connected to a computer (18) and a thermal control unit (14). The backplane (12) includes a plurality of seats (20) for releasably holding a plurality of modules (16). Each module holds a reactor vessel (30) that may be used to conduct experiments. A plurality of laboratory instruments, such as motors, switches, sensors and pumps are included within the backplane and on the reactor modules. These laboratory instruments are utilized to perform work on the contents of the reactor vessels (30) when the modules holding the reactor vessels (30) are positioned in the backplane (12). A computer (18) is connected to the backplane (12) and controls the laboratory instruments within the backplane (12) and on the reactor modules (30) positioned within the backplane (12). A thermal control unit (14) provides a thermal control fluid that is delivered to the reactors (30) in the reactor modules when the modules are properly seated in the backplane.
摘要翻译：模块化反应器系统（10）包括连接到计算机（18）和热控制单元（14）的背板（12）。背板（12）包括用于可释放地保持多个模块（16）的多个座（20）。每个模块都装有可用于进行实验的反应器容器（30）。多个实验室仪器，如电机，开关，传感器和泵都包含在背板和反应堆模块内。当保持反应容器（30）的模块位于背板（12）中时，这些实验室仪器用于对反应堆容器（30）的内容物进行工作。计算机（18）连接到背板（12）并且控制底板（12）内的实验室仪器和位于背板（12）内的反应堆模块（30）上。一个热控制单元（14）提供一个热控制流体，当这些模块正确地安置在背板中时，该热控制流体被输送到反应器模块中的反应器（30）。

7. 发明申请

WO2004062780A3 STIRRING SYSTEM 审中-公开
公开(公告)号：WO2004062780A3
公开(公告)日：2004-07-29
申请号：PCT/US2004/000166
申请日：2004-01-07
申请人： ARGONAUT TECHNOLOGIES, INC. , WASSON, James, R. , MELEVAGE, Paul , MEIER, Daniel, J.
发明人： WASSON, James, R. , MELEVAGE, Paul , MEIER, Daniel, J.
IPC分类号： B01F7/00
摘要： A modular reactor system comprises a backplane connected to a computer and a thermal control unit. The backplane includes a plurality of seats for releasably holding a plurality of modules. Each module holds a reactor vessel that may be used to conduct experiments. A plurality of laboratory instruments, such as motors, switches, sensors and pumps are included within the backplane and on the reactor modules. These laboratory instruments are utilized to perform work on the contents of the reactor vessels when the modules holding the reactor vessels are positioned in the backplane. A computer is connected to the backplane and controls the laboratory instruments within the backplane and on the reactor modules positioned within the backplane. A thermal control unit provides a thermal control fluid that is delivered to the reactors in the reactor modules when the modules are properly seated in the backplane.

8. 发明申请

WO2003015135A3 METHOD FOR FABRICATING A THIN-MEMBRANE STENCIL MASK AND METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
公开(公告)号：WO2003015135A3
公开(公告)日：2003-02-20
申请号：PCT/US2002/024164
申请日：2002-07-23
申请人： MOTOROLA, INC.
发明人： MANGAT, Pawitter , MOGAB, Joe , SMITH, Kenneth, H. , WASSON, James, R.
IPC分类号： G03F1/16
摘要： A stencil mask (12 or 12) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.

9. 发明申请

WO2003019290A3 PATTERNING AN INTEGRATED CIRCUIT USING A REFLECTIVE MASK 审中-公开
公开(公告)号：WO2003019290A3
公开(公告)日：2003-03-06
申请号：PCT/US2002/024628
申请日：2002-08-02
申请人： MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE
发明人： HAN, Sang-in, , MANGAT, Pawitter, , WASSON, James, R. , HECTOR, Scott, D.
IPC分类号： G03F1/14
摘要： A desired pattern is formed in a photoresist layer (170, 180) that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer (20), an absorber layer (30) and an anti-reflective (ARC) layer (40). The ARC layer (40) is patterned according to the desired pattern. The ARC layer (40) is inspected to find areas in which the desired pattern is not achieved. The ARC layer (40) is then repaired to achieve the desired pattern with the absorber layer (30) protecting the reflective layer (20). The desired pattern is transferred to the absorber layer (30) to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer (160) to expose the photoresist layer (170, 180) overlying the semiconductor wafer (160) with the desired pattern.

10. 发明申请

WO2003019290A2 AN INTEGRATED CIRCUIT USING A REFLECTIVE MASK 审中-公开
标题翻译：使用反射屏蔽的集成电路
公开(公告)号：WO2003019290A2
公开(公告)日：2003-03-06
申请号：PCT/US2002/024628
申请日：2002-08-02
申请人： MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE
发明人： HAN, Sang-in, , MANGAT, Pawitter, , WASSON, James, R. , HECTOR, Scott, D.
IPC分类号： G03F1/14
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/84
摘要： A desired pattern is formed in a photoresist layer (170, 180) that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer (20), an absorber layer (30) and an anti-reflective (ARC) layer (40). The ARC layer (40) is patterned according to the desired pattern. The ARC layer (40) is inspected to find areas in which the desired pattern is not achieved. The ARC layer (40) is then repaired to achieve the desired pattern with the absorber layer (30) protecting the reflective layer (20). The desired pattern is transferred to the absorber layer (30) to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer (160) to expose the photoresist layer (170, 180) overlying the semiconductor wafer (160) with the desired pattern.
摘要翻译：在使用反射掩模覆盖在半导体晶片上的光致抗蚀剂层（170,180）中形成期望的图案。该掩模通过连续沉积反射层（20），吸收层（30）和抗反射（ARC）层（40）而形成。根据期望的图案对ARC层（40）进行图案化。检查ARC层（40）以找到未实现所需图案的区域。然后修复ARC层（40）以使保护反射层（20）的吸收层（30）达到期望的图案。将期望的图案转移到吸收层（30）以露出掩模的反射部分。辐射从反射掩模反射到半导体晶片（160），以期望的图案露出覆盖半导体晶片（160）的光致抗蚀剂层（170,180）。

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