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1. 发明申请

WO2017082744A1 A METHOD FOR FORMING A LAMINATE FOR A PRINTED CIRCUIT BOARD 审中-公开
标题翻译：一种形成印刷电路板层压板的方法
公开(公告)号：WO2017082744A1
公开(公告)日：2017-05-18
申请号：PCT/PL2016/000122
申请日：2016-11-08
申请人： SKORUT SYSTEMY SOLARNE - SP. Z O. O.
发明人： STRUŚ, Wojciech , SKORUT, Artur
IPC分类号： H05K1/03 , H05K3/18 , H05K3/10 , H05K3/42 , H05K3/38 , H05K3/00
CPC分类号： H05K1/0373 , H05K1/0326 , H05K1/0366 , H05K3/0052 , H05K3/105 , H05K3/182 , H05K3/185 , H05K3/187 , H05K3/381 , H05K3/422 , H05K3/426 , H05K2201/0236 , H05K2203/0278 , H05K2203/107 , H05K2203/125
摘要： The present invention relates to the method for modification of laminates used to manufacture printed circuit boards. The present invention allows to use the laminates used in the subtractive method for industrial manufacturing of printed circuit boards in semi-additive and additive processes. Modification of laminates used to manufacture printed circuit boards consist in using two processes: 1. Adding to the resin comprising the laminate a catalytic substance that is a photoactive titanium dioxide or TiO 2 -Me n O type complex oxides in the amount of at least 10% by weight as compared to the resin weight, preferably from 10% to 40% by weight. 2. Development of the surface of the laminate manufactured in the first process to at least 150%. To obtain the required copper adhesion to the dielectric substrate, the process of photoselective plating is used. Photoselective plating is a process wherein metal is deposited only on those sections of the dielectric surface where exposure to light results in a metal formation reaction. The principle of photoselective plating is that during the exposure of the dielectric photosensitive material in the sections where absorption takes place, catalytic centres are created, the nucleation seeds on which metal is deposited later during chemical plating. Such a process results in formation of a pattern drawing on the board surface consisting of metal particles. The process of formation of the printed circuit board is carried out when two conditions are met by the used dielectric substrate, wherein the base laminate forming the basic component for the manufactured printed circuit board is properly prepared. The laminate intended for manufacturing printed circuit boards should undergo an additional two-track treatment during its formation. To the known and used in the state of the art dielectric laminates or other materials during their formation a component with a significant catalytic or photocatalytic activity is added with a later appropriate laminate surface development.
摘要翻译：本发明涉及用于修改用于制造印刷电路板的层压板的方法。本发明允许使用减成法中使用的层压材料用于半加成和添加法工业制造印刷电路板。用于制造印刷电路板的层压材料的改进在于使用两种工艺：1.向包含层压材料的树脂添加作为光敏二氧化钛或TiO 2 -Me 2 N 3的催化物质，与树脂重量相比，其量为至少10重量％，优选10重量％至40重量％。 2.在第一工艺中制造的层压板的表面发展至少150％。为了获得对电介质基底所需的铜附着力，使用了光选择性电镀工艺。光选择性电镀是这样一种工艺，其中金属仅沉积在电介质表面的暴露于光下的那些部分上导致金属形成反应。光选择性电镀的原理是，在介电光敏材料暴露于发生吸收的部分期间，产生催化中心，在化学镀期间在其上沉积金属的成核晶种。这种工艺导致在由金属颗粒组成的板表面上形成图案。印刷电路板的形成过程在所使用的电介质基板满足两个条件时进行，其中形成用于制造的印刷电路板的基本部件的基层压板被适当地制备。用于制造印刷电路板的层压板在其形成期间应该进行额外的双轨处理。对于现有技术中已知的和用于现有技术的电介质层压板或其他材料在形成期间，具有显着的催化或光催化活性的部件被添加以后适当的层压板表面显影。

2. 发明申请

WO2011034075A1 セラミックス回路基板及びその製造方法审中-公开
标题翻译：陶瓷电路板及其制造方法
公开(公告)号：WO2011034075A1
公开(公告)日：2011-03-24
申请号：PCT/JP2010/065914
申请日：2010-09-15
申请人：株式会社東芝 , 東芝マテリアル株式会社 , 加藤寛正
发明人：加藤　寛正
IPC分类号： H05K1/02 , H01L23/12 , H01L23/13 , H05K1/03 , H05K1/09 , H05K3/20 , H05K3/34
CPC分类号： H05K3/062 , B23K1/0016 , B23K2201/36 , C04B37/026 , C04B2235/658 , C04B2235/96 , C04B2235/9607 , C04B2237/125 , C04B2237/126 , C04B2237/127 , C04B2237/343 , C04B2237/366 , C04B2237/368 , C04B2237/706 , H01L21/44 , H01L23/15 , H01L23/3735 , H01L2924/0002 , H05K1/0306 , H05K3/06 , H05K3/067 , H05K3/202 , H05K3/3484 , H05K3/38 , H05K2201/0355 , H05K2203/013 , H05K2203/0392 , H05K2203/0465 , H05K2203/0545 , H05K2203/125 , H05K2203/167 , Y10T29/49156 , H01L2924/00
摘要：　本発明の実施形態によれば、セラミックス基板１と、銅回路板５と、ろう材はみ出し部４ａとを備えるセラミックス回路基板が提供される。銅回路板５は、セラミックス基板１の少なくとも一方の面に、Ａｇ、Ｃｕ及びＴｉを含むろう材層を介して接合されている。ろう材はみ出し部４ａは、銅回路板５の側面から外側にはみ出したろう材層で形成されている。ろう材はみ出し部４ａ中のＴｉ相およびＴｉＮ相の合計は３質量％以上で、かつセラミックス基板と銅回路板の間に介在されたろう材層４ｂ中のＴｉ相およびＴｉＮ相の合計量と異なっている。ろう材はみ出し部４ａにおける１個当たりの面積が２００μｍ２以下の空隙が１つ以下（０を含む）である。
摘要翻译：提供一种陶瓷电路板，包括陶瓷基体（1），铜电路板（5）和钎焊材料凸起部分（4a）。铜电路板（5）已经通过包含Ag，Cu和Ti的钎料层结合到陶瓷基体（1）的至少一个表面上。钎焊材料突出部（4a）由从铜电路板（5）的边缘向外突出的钎料层构成。钎焊材料突出部（4a）的Ti相和TiN相的总量为3质量％以上，与存在于钎焊材料层（4b）中的Ti相和TiN相的总量不同）介于陶瓷基座和铜电路板之间。存在于钎焊材料凸部（4a）中的面积为200μm2以下的空隙的个数为1个以下（包括0个）。

3. 发明申请

WO2004080139A1 METHOD FOR MANUFACTURING AN ELECTRICALLY CONDUCTIVE PATTERN 审中-公开
标题翻译：制造电导图案的方法
公开(公告)号：WO2004080139A1
公开(公告)日：2004-09-16
申请号：PCT/FI2003/000633
申请日：2003-08-29
申请人： RAFSEC OY , HUHTASALO, Lauri , STRÖMBERG, Samuli , HANHIKORPI, Marko
发明人： HUHTASALO, Lauri , STRÖMBERG, Samuli , HANHIKORPI, Marko
IPC分类号： H05K3/12
CPC分类号： H05K3/207 , G06K19/07779 , G06K19/07783 , H05K1/092 , H05K3/386 , H05K2203/016 , H05K2203/0278 , H05K2203/087 , H05K2203/102 , H05K2203/1157 , H05K2203/125 , Y10T29/49149 , Y10T29/49155
摘要： The present invention relates to a method for manufacturing an electrically conductive pattern by printing a layer comprising metal oxide on a carrier substrate (2) and reducing the metal oxide to metal. The reduced layer is transferred to an application substrate (7). The present invention also relates to the use of the method.
摘要翻译：本发明涉及通过在载体基板（2）上印刷包含金属氧化物的层并将金属氧化物还原成金属来制造导电图案的方法。还原层被转移到施加衬底（7）上。本发明还涉及该方法的用途。

4. 发明申请

WO1988003443A1 PROCESS FOR PREPARING MULTILAYER PRINTED CIRCUIT BOARDS 审中-公开
标题翻译：制备多层印刷电路板的方法
公开(公告)号：WO1988003443A1
公开(公告)日：1988-05-19
申请号：PCT/US1987002289
申请日：1987-09-10
申请人： MACDERMID, INCORPORATED
发明人： MACDERMID, INCORPORATED , RUSZCZYK, Stanley, J. , FERRIER, Donald, R. , LARSON, Gary, B. , GALLEGOS, Daniel , CASTALDI, Steven, A.
IPC分类号： B05D05/12
CPC分类号： H05K3/181 , H05K3/184 , H05K3/4602 , H05K3/4661 , H05K2201/0195 , H05K2201/0236 , H05K2203/1157 , H05K2203/125 , Y10S428/901
摘要： Multilayer printed circuit boards are fabricated by preparing a first layer in conventional manner by forming a resist image on a copper clad substrate, etching away unwanted copper, removing the resist from the circuit pattern and optionally applying a dielectric mask such as conventional solder mask to selected portions of the circuit pattern. A second layer, and optionally one or more subsequent layers, are fabricated by providing an image of a second circuit pattern in a predetermined location on said first layer, the image being formed using a suspension of cuprous oxide in a curable resin material. The image is cured at least partially and subjected to chemical reduction to convert at least a portion of the cuprous oxide to metallic copper. The image is then electrolessly plated with copper to build up the circuit pattern and the latter is selectively coated with a dielectric mask before repeating the cycle to build up one or more additional layers. Solder can be applied to selected areas of any of said printed circuit layers at any appropriate time during fabrication. The above method of fabrication has advantages of economy of time, materials and labor as compared with methods hitherto employed to prepare multilayer boards in which a plurality of single boards are fabricated individually and then assembled as a sandwich or laminate by application of heat and pressure.

5. 发明申请

WO2014133890A2 FUSED METAL NANOSTRUCTURED NETWORKS, FUSING SOLUTIONS WITH REDUCING AGENTS AND METHODS FOR FORMING METAL NETWORKS 审中-公开
标题翻译：熔融金属纳米结构网络，具有还原剂的熔融解决方案和形成金属网络的方法
公开(公告)号：WO2014133890A2
公开(公告)日：2014-09-04
申请号：PCT/US2014/017652
申请日：2014-02-21
申请人： C3NANO INC.
发明人： VIRKAR, Ajay , YANG, Xiqiang , LI, Ying-syi , MCKEAN, Dennis , LEMIEUX, Melburne, C.
IPC分类号： H03K17/96 , B32B5/02 , B32B15/02 , H05K1/02
CPC分类号： H03K17/9622 , B32B15/02 , B32B15/08 , B32B15/18 , B32B27/281 , B32B27/286 , B32B27/288 , B32B27/304 , B32B27/306 , B32B27/308 , B32B27/32 , B32B27/34 , B32B27/36 , B32B27/40 , B32B2270/00 , B32B2307/202 , B32B2307/412 , B32B2457/00 , C09D11/52 , G06F3/044 , G06F2203/04103 , G06F2203/04112 , H03K2217/96031 , H05K1/097 , H05K3/027 , H05K3/06 , H05K3/1283 , H05K2201/0108 , H05K2201/026 , H05K2203/107 , H05K2203/1131 , H05K2203/1157 , H05K2203/125 , Y10T428/12424 , Y10T428/12444 , Y10T442/655
摘要： Reduction/oxidation reagents have been found to be effective to chemically cure a sparse metal nanowire film into a fused metal nanostructured network through evidently a ripening type process. The resulting fused network can provide desirable low sheet resistances while maintaining good optical transparency. The transparent conductive films can be effectively applied as a single conductive ink or through sequential forming of a metal nanowire film with the subsequent addition of a fusing agent. The fused metal nanowire films can be effectively patterned, and the patterned films can be useful in devices, such as touch sensors.
摘要翻译：已经发现还原/氧化试剂通过明显的熟化方法将稀疏金属纳米线膜化学固化成熔融金属纳米结构网络是有效的。所得到的融合网络可以提供期望的低薄层电阻，同时保持良好的光学透明度。透明导电膜可以有效地作为单个导电油墨施加，或者通过随后添加熔融剂来连续地形成金属纳米线膜。熔融金属纳米线膜可以被有效地构图，并且图案化的膜可以用于诸如触摸传感器的器件中。

6. 发明申请

WO2014121156A1 GRAPHENE GROWTH ON SIDEWALLS OF PATTERNED SUBSTRATE 审中-公开
标题翻译：石墨基底上的石墨生长
公开(公告)号：WO2014121156A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/014342
申请日：2014-02-01
申请人： SOLAN, LLC , DAVIS, Mark, Alan
发明人： DAVIS, Mark, Alan
IPC分类号： H01L21/02 , H01L21/20 , H01L29/66
CPC分类号： C23C16/26 , G03F7/36 , H01L21/0237 , H01L21/02376 , H01L21/02381 , H01L21/02395 , H01L21/02491 , H01L21/02527 , H01L21/02587 , H01L21/02631 , H01L21/02645 , H01L21/76885 , H05K3/4007 , H05K2203/125
摘要： A method for forming a graphite-based structure comprises patterning a substrate thereby forming a plurality of elements, each respective element in the plurality of elements separated from an adjacent element by a corresponding trench in a plurality of trenches on the substrate. A first element in the plurality of elements has a first surface. A first trench in the plurality of trenches separates the first element from an adjacent element in the plurality of elements, and the first trench has a second surface. The first surface and the second surface are separated by a first side wall of the first element. The method further comprises creating a graphene initiating layer on the first side wall of the first element. The method also comprises generating graphene using the graphene initiating layer thereby forming the graphite-based structure.
摘要翻译：一种用于形成石墨基结构的方法，包括使衬底形成图案，从而形成多个元件，多个元件中的每个元件通过衬底上的多个沟槽中的相应沟槽与相邻元件分离。多个元件中的第一元件具有第一表面。多个沟槽中的第一沟槽将第一元件与多个元件中的相邻元件分开，并且第一沟槽具有第二表面。第一表面和第二表面由第一元件的第一侧壁分开。该方法还包括在第一元件的第一侧壁上创建石墨烯起始层。该方法还包括使用石墨烯起始层产生石墨烯，从而形成基于石墨的结构。

7. 发明申请

WO2013036519A1 CONDUCTIVE MATERIAL AND PROCESS 审中-公开
标题翻译：导电材料和工艺
公开(公告)号：WO2013036519A1
公开(公告)日：2013-03-14
申请号：PCT/US2012/053764
申请日：2012-09-05
申请人： HENKEL CORPORATION , WEI, Bin , HUANG, Xiaoyan , XIAO, Allison, Yue
发明人： WEI, Bin , HUANG, Xiaoyan , XIAO, Allison, Yue
IPC分类号： C09D11/00 , C09D11/10 , H01B1/22 , B41M5/00 , B41M7/00 , B05D3/06
CPC分类号： H05K3/027 , B41M5/0023 , C09D11/52 , H01B1/22 , H05K1/092 , H05K3/105 , H05K3/1283 , H05K2203/1131 , H05K2203/125
摘要： A method for making a conductive network of sintered silver comprises preparing a conductive ink comprising a silver compound and a binder; depositing the conductive ink on a substrate and applying an external energy source to the deposited conductive ink to dry the ink; and applying an external energy source to the dried ink to decompose the ink to elemental silver and to sinter the elemental silver into a conductive network.
摘要翻译：制造烧结银导电网络的方法包括制备包含银化合物和粘合剂的导电油墨; 将导电油墨沉积在基材上并将外部能量源施加到沉积的导电油墨上以干燥油墨; 以及将外部能量源施加到干燥的油墨上以将油墨分解成元素银并将元素银烧结成导电网络。

8. 发明申请

WO2010044904A1 METHOD FOR REDUCING THIN FILMS ON LOW TEMPERATURE SUBSTRATES 审中-公开
标题翻译：在低温基底上减薄薄膜的方法
公开(公告)号：WO2010044904A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/038289
申请日：2009-03-25
申请人： NCC NANO, LLC , POPE, Dave, S. , SCHRODER, Kurt, A. , RAWSON, Ian, M.
发明人： POPE, Dave, S. , SCHRODER, Kurt, A. , RAWSON, Ian, M.
IPC分类号： C23C18/00
CPC分类号： H05K3/105 , C23C18/1601 , C23C18/1658 , C23C18/1667 , C23C18/31 , H05K1/0393 , H05K2203/087 , H05K2203/1157 , H05K2203/125 , H05K2203/1545
摘要： A method for producing an electrically conductive thin film on a substrate is disclosed. Initially, a reducible metal compound and a reducing agent are dispersed in a liquid. The dispersion is then deposited on a substrate as a thin film. The thin film along with the substrate is subsequently exposed to a pulsed electromagnetic emission to chemically react with the reducible metal compound and the reducing agent such that the thin film becomes electrically conductive.
摘要翻译：公开了一种在基板上制造导电薄膜的方法。最初，还原性金属化合物和还原剂分散在液体中。然后将分散体作为薄膜沉积在基材上。随后将薄膜与衬底一起暴露于脉冲电磁发射以与可还原金属化合物和还原剂发生化学反应，使得薄膜变得导电。

9. 发明申请

WO2010026571A2 METAL NANOWIRE THIN-FILMS 审中-公开
标题翻译：金属纳米薄膜
公开(公告)号：WO2010026571A2
公开(公告)日：2010-03-11
申请号：PCT/IL2009/000842
申请日：2009-09-01
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD.
发明人： MARKOVICH, Gil , AZULAI, Daniel , KRICHEVSKI, Olga
IPC分类号： C23C18/14 , C23C18/16 , C23C18/34 , C23C18/40 , C23C18/44 , C23C18/48 , H05K3/18
CPC分类号： H05K1/09 , C23C18/14 , C23C18/166 , C23C18/1667 , C23C18/1676 , C23C18/34 , C23C18/40 , C23C18/44 , C23C18/48 , H01B1/02 , H01L29/786 , H05K1/0274 , H05K3/105 , H05K3/182 , H05K2201/0108 , H05K2201/0257 , H05K2201/026 , H05K2201/10121 , H05K2201/10128 , H05K2201/10166 , H05K2203/013 , H05K2203/1157 , H05K2203/125
摘要： A conductive nanowire film based on a high aspect-ratio metal is disclosed. The nanowire film is produced by inducing metal reduction in a concentrated surfactant solution containing metal precursor ions, a surfactant and a reducing agent. The metal nanostructures demonstrate utility in a great variety of applications.
摘要翻译：公开了基于高纵横比金属的导电纳米线膜。纳米线膜通过在含有金属前体离子，表面活性剂和还原剂的浓缩表面活性剂溶液中诱导金属还原来制备。金属纳米结构在各种应用中表现出实用性。

10. 发明申请

WO2007055223A1 金属膜形成方法及び金属パターン形成方法审中-公开
标题翻译：形成金属膜的方法和形成金属图案的方法
公开(公告)号：WO2007055223A1
公开(公告)日：2007-05-18
申请号：PCT/JP2006/322238
申请日：2006-11-08
申请人：富士フイルム株式会社 , 松本和彦
发明人：松本和彦
IPC分类号： C25D5/56 , C23C18/16 , C25D21/12 , H05K1/03 , H05K3/18 , C08F292/00 , C08J7/04
CPC分类号： H05K3/188 , C23C18/1653 , C23C18/1658 , C23C18/1834 , C23C18/2066 , C23C18/31 , C25D5/022 , C25D5/18 , C25D5/56 , H05K3/108 , H05K3/181 , H05K3/387 , H05K2203/1157 , H05K2203/125 , Y10T428/12063
摘要：　本発明は、（ａ１）基板上に、金属イオン又は金属塩と相互作用する官能基を有し該基板と直接化学結合するポリマーからなるポリマー層を設ける工程と、（ａ２）ポリマー層に金属イオン又は金属塩を付与する工程と、（ａ３）金属イオン又は金属塩を還元して、表面抵抗率が１０～１００ｋΩ／□の導電性層を形成する工程と、（ａ４）電気めっきにより、表面抵抗率が１×１０ -1 Ω／□以下の導電性層を形成する工程と、を有することを特徴とする金属膜形成方法、等を提供する。
摘要翻译：公开了一种形成金属膜的方法，其特征在于包括步骤（a1），用于在基材上形成由具有与金属离子或金属盐相互作用的官能团的聚合物构成的聚合物层，并且化学直接粘合到基材上; 用于向聚合物层提供金属离子或金属盐的步骤（a2）; 用于形成表面电阻率为10-100KO /□的导电层的步骤（a3）通过还原金属离子或金属盐; 以及用于形成表面电阻率为1×10 -1 O /λ的导电层的步骤（a4）或更少的电镀。

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