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1. 发明申请

WO2016090353A2 LOAD CURRENT COMPENSATION FOR ANALOG INPUT BUFFERS 审中-公开
标题翻译：模拟输入缓冲器的负载电流补偿
公开(公告)号：WO2016090353A2
公开(公告)日：2016-06-09
申请号：PCT/US2015/064191
申请日：2015-12-07
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SAKURAI, Satoshi
CPC分类号： H03M1/1245 , G11C27/02 , G11C27/026 , H03K19/01812 , H03M1/12
摘要： In described examples of systems and methods for load current compensation for analog input buffers, an input buffer (300) may include: a first transistor (Q 1 ) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q 2 ) having a collector terminal coupled to an emitter terminal of the first transistor (Q 1 ); a third transistor (Q 3 ) having an emitter terminal coupled to an emitter terminal of the second transistor (Q 2 ) and to a ground node, a collector terminal coupled to a current source (I bias ), and a base terminal coupled to the collector terminal and to a base terminal of the second transistor (Q 2 ); and a capacitor (C 1 ) coupled to the base terminals of the second and third transistors (Q 2 and Q 3 ) and to a second input node (v inn ), wherein the first and second input nodes (v inp and V inn ) are differential inputs.
摘要翻译：在所描述的用于模拟输入缓冲器的负载电流补偿的系统和方法的示例中，输入缓冲器（300）可以包括：第一晶体管（Q 1），其具有集电极耦合到电源节点的基极和耦合到第一输入节点（vinp）的基极; 具有耦合到第一晶体管（Q 1）的发射极端子的集电极端子的第二晶体管（Q 2）具有耦合到第二晶体管（Q 2）的发射极端子的发射极端子和接地节点的第三晶体管（Q 3），集电极端子耦合到第二晶体管电流源（I bias），以及耦合到集电极端子和第二晶体管（Q 2）的基极端子的基极端子; 和耦合到第二和第三晶体管（Q 2和Q 3）的基极端的电容器（C 1）以及耦合到第二和第三晶体管（Q 2和Q 3）的基极端的电容器输入节点（v inn），其中第一和第二输入节点（v inp和v inn）是差分输入。

2. 发明申请

WO2005109462A3 APPARATUS AND METHOD FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL 审中-公开
标题翻译：将信号从第一参考电平移位到第二参考电平的装置和方法
公开(公告)号：WO2005109462A3
公开(公告)日：2006-02-09
申请号：PCT/US2005015353
申请日：2005-05-02
申请人： TEXAS INSTRUMENTS INC , FATTARUSO JOHN W , SHEAHAN BENJAMIN J
发明人： FATTARUSO JOHN W , SHEAHAN BENJAMIN J
IPC分类号： H01H83/00 , H03K17/0412 , H03K19/003 , H03K19/013 , H03K19/018 , H03K19/0175
CPC分类号： H03K19/0136 , H03K17/04126 , H03K19/00346 , H03K19/00376 , H03K19/01812 , Y10T307/826
摘要： A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q
摘要翻译：电平移位装置80包括输入部分82，电平移位部分84和输出部分86.输入部分82的输入端子100,102处的从上游数据源接收的差分信令输入信号与公共发射极NPN的相应基极耦合双极晶体管Q1，Q2并分别呈现在集电极输出124,126至电平移位部分84.每个电平移位部分84包括低速网络130和高速网络140，高速网络140基本上并联耦合在相应的输出124,126和输出轨迹88.低速网络130作为电平设置信号路径操作，以将输出轨迹88处的DC（直流）电平设置为期望的电平。低速网络130采用有源放大器组件来设置输出直流电阻。在一个实施例中，有源分量是NPN双极晶体管Q

3. 发明申请

WO2005109462A2 APPARATUS AND METHOD FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL 审中-公开
标题翻译：将信号从第一参考电平移位到第二参考电平的装置和方法
公开(公告)号：WO2005109462A2
公开(公告)日：2005-11-17
申请号：PCT/US2005/015353
申请日：2005-05-02
申请人： TEXAS INSTRUMENTS INCORPORATED , FATTARUSO, John, W. , SHEAHAN, Benjamin, J.
发明人： FATTARUSO, John, W. , SHEAHAN, Benjamin, J.
IPC分类号： H01H83/00
CPC分类号： H03K19/0136 , H03K17/04126 , H03K19/00346 , H03K19/00376 , H03K19/01812 , Y10T307/826
摘要： A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q 4 configured as an emitter-follower, with its base connected to an output 124, 126 via a resistor R LS . High speed network 140 operates as a signal transition path to speed up provision of signal transitions (for example, information bearing signal transitions) to output locus 88. In one embodiment, a base 142 of an NPN bipolar transistor Q 5 is driven without added series resistance to avoid delay and unwanted filtering. Output section 86 connects signals appearing at output locus 88 with downstream portions of a communication system.
摘要翻译：电平移位装置80包括输入部分82，电平移位部分84和输出部分86.输入部分82的输入端子100,102处的从上游数据源接收的差分信令输入信号与公共发射极NPN的相应基极耦合双极晶体管Q1，Q2并分别呈现在集电极输出124,126至电平移位部分84.每个电平移位部分84包括低速网络130和高速网络140，高速网络140基本上并联耦合在相应的输出124,126和输出轨迹88.低速网络130作为电平设置信号路径操作，以将输出轨迹88处的DC（直流）电平设置为期望的电平。低速网络130采用有源放大器组件来设置输出直流电阻。在一个实施例中，有源部件是被配置为射极跟随器的NPN双极晶体管Q4，其基极通过电阻器RLS连接到输出端124,126。高速网络140作为信号转换路径进行操作，以加速提供信号转换（例如，信息承载信号转换）到输出轨迹88.在一个实施例中，NPN双极晶体管Q5的基极142被驱动而不增加串联电阻以避免延迟和不需要的过滤。输出部86将出现在输出轨迹88处的信号与通信系统的下游部分连接。

4. 发明申请

WO2005043761A1 SCHALTUNGSSYSTEM 审中-公开
标题翻译：交换系统
公开(公告)号：WO2005043761A1
公开(公告)日：2005-05-12
申请号：PCT/EP2004/009061
申请日：2004-08-12
申请人： INFINEON TECHNOLOGIES AG , KUZMENKA, Maksim , MUFF, Simon , RUCKERBAUER, Hermann
发明人： KUZMENKA, Maksim , MUFF, Simon , RUCKERBAUER, Hermann
IPC分类号： H03K19/003
CPC分类号： H03K19/018514 , H03K19/0175 , H03K19/01812
摘要： Ein Schaltungssystem weist eine Einrichtung (102) zum Ansteuern einer ersten und einer zweiten Speichereinheit mittels eines differentiellen Ansteuersignals auf. Das differentielle Ansteuerungssignal weist ein erstes Ansteuersignal und ein zweites, zu dem ersten Ansteuersignal invertiertes, Ansteuerungssignal auf. Ferner weist das Schaltungssystem eine differentielle Ansteuersignalleitung 120, die eine erste Signalleitung (122) zum Führen des ersten Ansteuersignals und eine zweite Signalleitung (124) zum Führen des zweiten Ansteuersignals aufweist auf. Die erste Schalteinheit (104) ist über die erste Signalleitung (122) und die zweite Schaltungseinheit (106) ist über die zweite Signalleitung (124) mit der Einrichtung (102) zum Ansteuern verbunden.
摘要翻译：一种电路系统，包括用于通过差分驱动信号的装置驱动的第一和第二存储器单元装置（102）。所述差动控制信号具有第一驱动器和第二反相为第一驱动信号，驱动信号。此外，电路系统到差分驱动信号线120，其具有用于引导所述第一驱动信号和用于引导所述第二驱动信号的第二信号线（124）的第一信号线（122）。经由第一信号线（122）和第二电路单元（106），所述第一开关单元（104）通过与用于驱动所述装置（102）的第二信号线（124）相连接。

5. 发明申请

WO1985002507A1 TEMPERATURE COMPENSATED TTL TO ECL TRANSLATOR 审中-公开
标题翻译：温度补偿TTL到ECL转换器
公开(公告)号：WO1985002507A1
公开(公告)日：1985-06-06
申请号：PCT/US1984001873
申请日：1984-11-16
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , ALLEN, Michael , YANG, Tsen-Shau
IPC分类号： H03K19/092
CPC分类号： H03K19/00376 , H03K19/01812
摘要： A temperature compensated differential level shift circuit (Fig. 2). An ECL type buffered differential circuit employs a source of threshold voltage, VT (Fig. 3), which matches the temperature-dependent characteristic of the input section of the level shift circuit. In a preferred embodiment, s Schottky diode (52) is provided in the output section of a bandgap reference voltage generator (Fig. 3) which matches the temperature dependence of a Schottky diode (30) in the input section of the level shift circuit (Fig. 2). As temperature shifts, the threshold voltage will shift in a manner that tracks the temperature-produced shift in the input voltage as it passes through the Schottky diode in the input section of the level shift circuit. Matched PNP or NPN transistors (70, 72 and 71, 73 ) may also be used in the input section of the level shift circuit (Figs. 6A, 7A) and in the output section of the bandgap reference voltage generator (Figs. 6B, 7B).

6. 发明申请

WO2016090353A3 LOAD CURRENT COMPENSATION FOR ANALOG INPUT BUFFERS 审中-公开
标题翻译：模拟输入缓冲器的负载电流补偿
公开(公告)号：WO2016090353A3
公开(公告)日：2016-12-01
申请号：PCT/US2015064191
申请日：2015-12-07
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN
发明人： SAKURAI SATOSHI
IPC分类号： H03M1/12 , G11C27/02 , H03K19/018
CPC分类号： H03M1/1245 , G11C27/02 , G11C27/026 , H03K19/01812 , H03M1/12
摘要： In described examples of systems and methods for load current compensation for analog input buffers, an input buffer (300) may include: a first transistor (Q1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q2) having a collector terminal coupled to an emitter terminal of the first transistor (Q1); a third transistor (Q3) having an emitter terminal coupled to an emitter terminal of the second transistor (Q2) and to a ground node, a collector terminal coupled to a current source (Ibias), and a base terminal coupled to the collector terminal and to a base terminal of the second transistor (Q2); and a capacitor (C1) coupled to the base terminals of the second and third transistors (Q2 and Q3) and to a second input node (vinn), wherein the first and second input nodes (vinp and Vinn) are differential inputs.
摘要翻译：在所描述的用于模拟输入缓冲器的负载电流补偿的系统和方法的示例中，输入缓冲器（300）可以包括：第一晶体管（Q1），其具有耦合到电源节点的集电极端子和耦合到第一输入端节点（vinp）; 第二晶体管（Q2），其具有耦合到所述第一晶体管（Q1）的发射极端子的集电极端子; 第三晶体管（Q3），其具有耦合到第二晶体管（Q2）的发射极端子和接地节点的发射极端子，耦合到电流源（Ibias）的集电极端子和耦合到集电极端子的基极端子，以及到所述第二晶体管（Q2）的基极端子; 以及耦合到第二和第三晶体管（Q2和Q3）的基极端子和第二输入节点（vinn）的电容器（C1），其中第一和第二输入节点（vin和Vinn）是差分输入。

7. 发明申请

WO1986002792A1 INTEGRATED CIRCUIT DEVICE ACCEPTING INPUTS AND PROVIDING OUTPUTS AT THE LEVELS OF DIFFERENT LOGIC FAMILIES 审中-公开
标题翻译：集成电路设备接收输入和提供不同逻辑系统级别的输出
公开(公告)号：WO1986002792A1
公开(公告)日：1986-05-09
申请号：PCT/US1984001805
申请日：1984-11-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , THOMPSON, Michael, D.
IPC分类号： H03K19/092
CPC分类号： H03K19/01812 , H01L27/0207 , H03K19/173
摘要： An integrated circuit device (10 in Fig. 2; 105 in Fig. 5) containing internal logic and/or memory circuitry (19; 114, 115) is provided with means to receive multiple inputs at the voltage levels of different logic families (Pi-Pi) and with means to provide multiple outputs at the voltage levels of different logic families (Pj-Pn). On-chip input translators (15, 17; 106, 108, 110, 112) receive the inputs at the level of a given logic family and translate to the level required by the internal logic and/or memory circuitry. After performance of logic and/or memory functions, on-chip output translators (16, 18; 107, 109, 111, 113) translate the otput of the internal logic and/or memory circuitry and provide external outputs at the voltage levels of different logic families. The internal logic and/or memory circuitry may be of a single logic family or may be composed of several logic families. On-chip translators may also be added between internal logic and/or memory circuitry of different families (116, 117).
摘要翻译：包含内部逻辑和/或存储器电路（19; 114,115）的集成电路器件（图2中的10;图5中的105）被提供有用于在不同逻辑系列的电压电平 -Pi），并且具有在不同逻辑系列（Pj-Pn）的电压电平处提供多个输出的装置。片上输入转换器（15,17; 106,108,110,112）在给定逻辑系列的电平处接收输入并转换为内部逻辑和/或存储器电路所需的电平。在执行逻辑和/或存储器功能之后，片上输出转换器（16,18; 107,109,111,113）转换内部逻辑和/或存储器电路的输出，并以不同的电压电平提供外部输出逻辑家庭内部逻辑和/或存储器电路可以是单个逻辑系列，或者可以由多个逻辑系列组成。片上翻译器也可以被添加到不同族（116,117）的内部逻辑和/或存储器电路之间。

8. 发明申请

WO0193491A3 HIGH FREQUENCY NETWORK TRANSMITTER 审中-公开
标题翻译：高频网络发射机
公开(公告)号：WO0193491A3
公开(公告)日：2003-09-04
申请号：PCT/US0118031
申请日：2001-06-04
申请人： CONNECTCOM MICROSYSTEMS INC
发明人： ENAM SYED KHURSHEED
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05 , H03K19/0175 , H03L7/00 , H03M9/00 , H04L7/02
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： A high frequency network transmitter receives a parallel input data stream and serializes the parallel input data stream for high speed transmission in a network. A phase alignment circuit aligns the parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock. A phase frequency detector in a clock multiply unit of the transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. A voltage controlled oscillator in the clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. A high-speed output driver produces a fast differential output signal for the serial transmitter. The output driver includes a first stage circuit which comprises a first active element to pull the first stage circuit output to a logic high and a second active element to pull the first stage circuit output to a logic low. The first stage circuit drives a second stage circuit which reacts relatively quickly to signal transitions by steering substantially constant current between differential pair transistors.
摘要翻译：高频网络发射机接收并行输入数据流，并串行化并行输入数据流，以在网络中进行高速传输。在使用第二传输时钟转换为串行输出数据流之前，相位对准电路将并行输入数据流对准第一传输时钟。发射机的时钟乘法单元中的相位频率检测器检测参考时钟和由时钟乘法单元产生的内部时钟之间的相位和频率差异。相位频率检测器包括复位电路，其增加了相位频率检测器的灵敏度和可靠性，从而允许相位频率检测器以高速运行。时钟倍增单元中的压控振荡器包括由多个相应的控制电压信号控制的多个变容二极管。多个变容二极管允许组合有效的方法来设置压控振荡器的输出信号频率。高速输出驱动器为串行发送器产生快速差分输出信号。输出驱动器包括第一级电路，其包括将第一级电路输出拉至逻辑高电平的第一有源元件和将第一级电路输出拉至逻辑低的第二有源元件。第一级电路驱动第二级电路，其通过在差分对晶体管之间转向基本恒定的电流来相对较快地对信号转换作出反应。

9. 发明申请

WO0195552A3 HIGH FREQUENCY NETWORK RECEIVER 审中-公开
标题翻译：高频网络接收器
公开(公告)号：WO0195552A3
公开(公告)日：2003-07-17
申请号：PCT/US0117962
申请日：2001-06-04
申请人： CONNECTCOM MICROSYSTEMS INC
发明人： ENAM SYED KYURSHEED
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05 , H03D13/00
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that allow a comparison of phase between a clock signal (326) and a serial bitstream (320). A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream (320) in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop (306). The phase-locked loop (306) can generate partially demultiplexed data (324), which is provided as an input to a demultiplexer (310). A framer circuit (312) searches demultiplexed data (328) for frame patterns and aligns the demultiplexed data (328). An acquisition aid circuit (308) indicates whether the clock signal (326) and a reference clock signal (332) are within a predetermined range.
摘要翻译：本发明涉及允许比较时钟信号（326）和串行比特流（320）之间的相位的方法和装置。相位检测器在相对固定的窗口中将串行位流（320）的相邻位或连续位之间的转换的一部分进行积分。有利地，相对固定的窗口允许在相对较高的频率（例如以SONET的OC-192速率）进行操作。整合结果包含在一个逻辑状态下花费在窗口内的时间量。整合结果保持到确定集成位的逻辑电平为止。逻辑电平转换的指示用于将积分结果与集成窗口内的转换时序联系起来。可以集成多个位转换，与定时信息相关，相加并作为输入提供给例如锁相环（306）中的压控振荡器。锁相环（306）可以产生部分解复用的数据（324），其作为输入提供给解复用器（310）。成帧器电路（312）搜索用于帧模式的解复用数据（328）并对准解复用数据（328）。获取辅助电路（308）指示时钟信号（326）和参考时钟信号（332）是否在预定范围内。

10. 发明申请

WO01095552A2 HIGH FREQUENCY NETWORK RECEIVER 审中-公开
标题翻译：高频网络接收器
公开(公告)号：WO01095552A2
公开(公告)日：2001-12-13
申请号：PCT/US2001/017962
申请日：2001-06-04
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that allow a comparison of phase between a clock signal (326) and a serial bitstream (320). A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream (320) in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop (306). The phase-locked loop (306) can generate partially demultiplexed data (324), which is provided as an input to a demultiplexer (310). A framer circuit (312) searches demultiplexed data (328) for frame patterns and aligns the demultiplexed data (328). An acquisition aid circuit (308) indicates whether the clock signal (326) and a reference clock signal (332) are within a predetermined range.
摘要翻译：本发明涉及允许比较时钟信号（326）和串行比特流（320）之间的相位的方法和装置。相位检测器在相对固定的窗口中将串行位流（320）的相邻位或连续位之间的转换的一部分进行积分。有利地，相对固定的窗口允许在相对较高的频率（例如以SONET的OC-192速率）进行操作。整合结果包含在一个逻辑状态下花费在窗口内的时间量。整合结果保持到确定集成位的逻辑电平为止。逻辑电平转换的指示用于将积分结果与集成窗口内的转换时序联系起来。可以集成多个位转换，与定时信息相关，相加并作为输入提供给例如锁相环（306）中的压控振荡器。锁相环（306）可以产生部分解复用的数据（324），其作为输入提供给解复用器（310）。成帧器电路（312）搜索用于帧模式的解复用数据（328）并对准解复用数据（328）。获取辅助电路（308）指示时钟信号（326）和参考时钟信号（332）是否在预定范围内。

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