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1. 发明申请

WO1996008871A1 CONTROLLED SLEW RATE OUTPUT BUFFER 审中-公开
标题翻译：控制的速度输出缓冲器
公开(公告)号：WO1996008871A1
公开(公告)日：1996-03-21
申请号：PCT/US1995011718
申请日：1995-09-14
申请人： MICROUNITY SYSTEMS ENGINEERING, INC. , CAMPBELL, John, G. , WONG, Ban, Pak
发明人： MICROUNITY SYSTEMS ENGINEERING, INC.
IPC分类号： H03K19/0175
CPC分类号： H03K19/0136 , H03K19/00353 , H03K19/017581
摘要： An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor (Q1, Q2) coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices (N5-N8) coupled between the common output node and the base of the pull-down bipolar transistor (Q2). A second set of parallel MOS devices (P1-P4) are coupled between the base of the pull-up output stage bipolar transistor (Q1) and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.
摘要翻译：公开了一种控制其输出信号的转换速率的输出缓冲器。该缓冲器包括一个上拉电阻和一个下拉双极晶体管（Q1，Q2），耦合在VDD和VSS之间串联的公共输出节点。缓冲器还包括耦合在公共输出节点和下拉双极晶体管（Q2）的基极之间的第一组并联MOS器件（N5-N8）。第二组并联MOS器件（P1-P4）耦合在上拉输出级双极晶体管（Q1）的基极和VDD之间。每组MOS器件的栅极耦合到数字选择信号。每个上拉和下拉晶体管（当它们被使能时）驱动基极的电流量由数字选择信号使能的MOS器件的数量决定。因此，本发明的缓冲器能够调节其输出信号的转换速率以适应耦合到公共输出节点的不同负载。

2. 发明申请

WO2005109462A3 APPARATUS AND METHOD FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL 审中-公开
标题翻译：将信号从第一参考电平移位到第二参考电平的装置和方法
公开(公告)号：WO2005109462A3
公开(公告)日：2006-02-09
申请号：PCT/US2005015353
申请日：2005-05-02
申请人： TEXAS INSTRUMENTS INC , FATTARUSO JOHN W , SHEAHAN BENJAMIN J
发明人： FATTARUSO JOHN W , SHEAHAN BENJAMIN J
IPC分类号： H01H83/00 , H03K17/0412 , H03K19/003 , H03K19/013 , H03K19/018 , H03K19/0175
CPC分类号： H03K19/0136 , H03K17/04126 , H03K19/00346 , H03K19/00376 , H03K19/01812 , Y10T307/826
摘要： A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q
摘要翻译：电平移位装置80包括输入部分82，电平移位部分84和输出部分86.输入部分82的输入端子100,102处的从上游数据源接收的差分信令输入信号与公共发射极NPN的相应基极耦合双极晶体管Q1，Q2并分别呈现在集电极输出124,126至电平移位部分84.每个电平移位部分84包括低速网络130和高速网络140，高速网络140基本上并联耦合在相应的输出124,126和输出轨迹88.低速网络130作为电平设置信号路径操作，以将输出轨迹88处的DC（直流）电平设置为期望的电平。低速网络130采用有源放大器组件来设置输出直流电阻。在一个实施例中，有源分量是NPN双极晶体管Q

3. 发明申请

WO2005109462A2 APPARATUS AND METHOD FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL 审中-公开
标题翻译：将信号从第一参考电平移位到第二参考电平的装置和方法
公开(公告)号：WO2005109462A2
公开(公告)日：2005-11-17
申请号：PCT/US2005/015353
申请日：2005-05-02
申请人： TEXAS INSTRUMENTS INCORPORATED , FATTARUSO, John, W. , SHEAHAN, Benjamin, J.
发明人： FATTARUSO, John, W. , SHEAHAN, Benjamin, J.
IPC分类号： H01H83/00
CPC分类号： H03K19/0136 , H03K17/04126 , H03K19/00346 , H03K19/00376 , H03K19/01812 , Y10T307/826
摘要： A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q 4 configured as an emitter-follower, with its base connected to an output 124, 126 via a resistor R LS . High speed network 140 operates as a signal transition path to speed up provision of signal transitions (for example, information bearing signal transitions) to output locus 88. In one embodiment, a base 142 of an NPN bipolar transistor Q 5 is driven without added series resistance to avoid delay and unwanted filtering. Output section 86 connects signals appearing at output locus 88 with downstream portions of a communication system.
摘要翻译：电平移位装置80包括输入部分82，电平移位部分84和输出部分86.输入部分82的输入端子100,102处的从上游数据源接收的差分信令输入信号与公共发射极NPN的相应基极耦合双极晶体管Q1，Q2并分别呈现在集电极输出124,126至电平移位部分84.每个电平移位部分84包括低速网络130和高速网络140，高速网络140基本上并联耦合在相应的输出124,126和输出轨迹88.低速网络130作为电平设置信号路径操作，以将输出轨迹88处的DC（直流）电平设置为期望的电平。低速网络130采用有源放大器组件来设置输出直流电阻。在一个实施例中，有源部件是被配置为射极跟随器的NPN双极晶体管Q4，其基极通过电阻器RLS连接到输出端124,126。高速网络140作为信号转换路径进行操作，以加速提供信号转换（例如，信息承载信号转换）到输出轨迹88.在一个实施例中，NPN双极晶体管Q5的基极142被驱动而不增加串联电阻以避免延迟和不需要的过滤。输出部86将出现在输出轨迹88处的信号与通信系统的下游部分连接。

4. 发明申请

WO1985004774A1 TEMPERATURE TRACKING AND SUPPLY VOLTAGE INDEPENDENT LINE DRIVER FOR ECL CIRCUITS 审中-公开
标题翻译：用于ECL电路的温度跟踪和供电电压独立线驱动器
公开(公告)号：WO1985004774A1
公开(公告)日：1985-10-24
申请号：PCT/US1985000483
申请日：1985-03-19
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , MA, Bing-Fong
IPC分类号： H03K19/086
CPC分类号： H03K19/0136 , H03K19/086
摘要： An active pulldown means is provided for the output line of an ECL gate (Figures 3-5). The pulldown means (46, 57, 60 and 62) utilizes a Wilson current mirror (51, 52, 54 and 55) as a differential-to-single ended converter in a transition detection arrangement which tracks temperature variations and rejects supply voltage transients in order to ensure correct operation under all conditions. The desired and the present output conditions are compared in the detection scheme. High transient current is supplied to the output only when the two output conditions do not match for output hing-to-low transitions.

5. 发明申请

WO99031802A1 OUTPUT DRIVER CIRCUIT WITH JUMP START FOR CURRENT SINK ON DEMAND 审中-公开
标题翻译：输出驱动电路，采用跳闸开始，以满足当前需求
公开(公告)号：WO99031802A1
公开(公告)日：1999-06-24
申请号：PCT/IB1998/001533
申请日：1998-10-05
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/003 , H03K19/013
CPC分类号： H03K19/00353 , H03K19/001 , H03K19/0136
摘要： An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value. A jump start circuit having a second current path with a lower impedance than the first current path charges the control terminal of the feeder transistor to said threshold faster than said first path and is disabled when the voltage at the ouput node falls below about the first value, thereby saving power.
摘要翻译：用于将逻辑电路耦合到负载的输出驱动器电路包括输入节点，用于耦合到负载的输出节点和用于响应于在输入节点接收的信号对输出节点进行放电的下拉开关。电流吸收电路包括馈电晶体管，当输出节点处的电压超过逻辑高电平和逻辑低电平之间的第一阈值时，该馈电晶体管向下拉开关的控制端提供电流，以使下拉开关导通。馈电晶体管由具有第一阻抗的第一充电路径充电，通过该第一充电路径需要第一时间段以使下拉开关导通，当输出节点处的电压低于第一阻抗时，第一阻抗提供低待机电流值。具有比第一电流路径低的阻抗的第二电流路径的跳转启动电路将馈电晶体管的控制端子充电到比所述第一路径更快的阈值，并且当输出节点处的电压低于约第一值时禁用，从而节约电力。

6. 发明申请

WO1995013657A1 BI-MODE CIRCUIT FOR DRIVING AN OUTPUT LOAD 审中-公开
标题翻译：用于驱动输出负载的双模电路
公开(公告)号：WO1995013657A1
公开(公告)日：1995-05-18
申请号：PCT/US1994003952
申请日：1994-04-12
申请人： LINFINITY MICROELECTRONICS INC.
发明人： LINFINITY MICROELECTRONICS INC. , AGIMAN, Dan
IPC分类号： H03K17/04
CPC分类号： H03K19/0136
摘要： A bi-mode circuit for driving a capacitive output load (12) selectively couples the output load (12) to a power supply voltage source (26) or to a low discharge voltage source (22) such as ground using switches (SW1, SW2, SW3) which are controlled by an input buffer (44) in response to an input signal (42). When the input signal (42) becomes high, rapid pull-down of a capacitive output load (12) is achieved using a high internal pre-drive current provided by the first and second current amplifiers (Q96, Q95) in a first mode of the operation. As the output voltage decreases, turnoff of the first current amplifier (Q96) is prevented by switching to a second mode when the output voltage drops below a threshold value as determined by a comparator (56).
摘要翻译：用于驱动电容性输出负载（12）的双模电路选择性地将输出负载（12）耦合到电源电压源（26）或使用开关（SW1，SW2）的低放电电压源（22），SW3），其由输入缓冲器（44）响应于输入信号（42）控制。当输入信号（42）变高时，使用由第一和第二电流放大器（Q96，Q95）提供的第一和第二电流放大器（Q96，Q95）提供的高内部预驱动电流来实现电容性输出负载（12）的快速下拉的操作。当输出电压降低时，当比较器（56）确定输出电压下降到低于阈值时，通过切换到第二模式来防止第一电流放大器（Q96）的关断。

7. 发明申请

WO1994005085A1 BICMOS ECL-TO-CMOS LEVEL TRANSLATOR AND BUFFER 审中-公开
标题翻译： BICMOS ECL-to-CMOS电平转换器和缓冲器
公开(公告)号：WO1994005085A1
公开(公告)日：1994-03-03
申请号：PCT/US1993005106
申请日：1993-05-28
申请人： MICROUNITY SYSTEMS ENGINEERING, INC.
发明人： MICROUNITY SYSTEMS ENGINEERING, INC. , WONG, Ban, Pak
IPC分类号： H03K19/0944
CPC分类号： H03K19/018521 , H03K19/00361 , H03K19/0136 , H03K19/017518
摘要： An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.
摘要翻译：描述了ECL到CMOS电平转换器和BiCMOS缓冲器。从第一输入PMOS晶体管（P1）提供的电流是包括第一和第二NMOS晶体管（N1和N2）的电流镜的输入电流。当前镜像控制翻译器的当前采样和下载功能。第三和第四NMOS晶体管（N3和N4）耦合到电流镜中的第一和第二NMOS晶体管，并且用于改变第一和第二NMOS晶体管的源极体电压，并因此改变其增益，从而导致电流增加驱动和下沉能力。本发明的BiCMOS差分缓冲器在第一和第二输出节点（115和215）上提供差分输出信号。它由第一和第二交叉耦合缓冲器（100B和200B）组成。交叉耦合缓冲区导致改进的高到低的转换时间。

8. 发明申请

WO1997018632A1 AN ACTIVE PULL-DOWN CIRCUIT FOR ECL USING A CAPACITIVE-DISCHARGE COUPLED CHARGE PUMP 审中-公开
标题翻译：使用电容式放电耦合充电泵的ECL的主动上拉电路
公开(公告)号：WO1997018632A1
公开(公告)日：1997-05-22
申请号：PCT/US1996018150
申请日：1996-11-13
申请人： TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
发明人： TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. , HARR, Jerome, D.
IPC分类号： H03K19/086
CPC分类号： H03K19/0136 , H03K19/086
摘要： Fast fall times for ECL logic waveforms are produced by use of a charge pump, which very quickly transfers charge from the ECL output load capacitance (7) into a temporary holding capacitor (CREG). The charge transferred onto the temporary holding capacitor (CREG) may then be removed at a leisurely pace. The charge pump includes a pulldown transistor (Q8), and a control circuit that selectively turns the pulldown transistor on, if the ECL ouptut will be low, or off, if the ECL output will be high. The control circuit includes an emitter-follower transistor (Q9) which follows the differential ECL collector node that changes voltage inversely to the desired final ECL output. A diode (D10) is connected to the emitter-follower transistor's emitter so that the diode output is two diode drops below the inverse ECL collector node. The diode (D10) drives the base of the pulldown transistor, so that the base of the pulldown transistor remains static until the inputs to the circuit change.
摘要翻译： ECL逻辑波形的快速下降时间通过使用电荷泵产生，电荷泵非常快速地将电荷从ECL输出负载电容（7）传送到临时保持电容（CREG）。然后转移到临时保持电容器（CREG）上的电荷可以以悠闲的速度被移除。电荷泵包括一个下拉晶体管（Q8），以及一个控制电路，如果ECL输出为低电平，则选择性地将下拉晶体管导通，如果ECL输出为高电平。控制电路包括发射极跟随器晶体管（Q9），该晶体管跟随ECL收集节点，将电压与期望的最终ECL输出相反地改变。二极管（D10）连接到射极跟随器晶体管的发射极，使得二极管输出为低于反向ECL收集器节点的二极管。二极管（D10）驱动下拉晶体管的基极，使得下拉晶体管的基极保持静止，直到电路的输入变化。

9. 发明申请

WO1990002448A1 A BICMOS INVERTER CIRCUIT 审中-公开
标题翻译： BICMOS逆变器电路
公开(公告)号：WO1990002448A1
公开(公告)日：1990-03-08
申请号：PCT/US1989002865
申请日：1989-07-05
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , BUSHEY, Thomas, P.
IPC分类号： H03K17/12
CPC分类号： H03K5/151 , H03K19/0136 , H03K19/017518 , H03K19/09448
摘要： A BICMOS inverter circuit having a high input impedance, improved switching characteristics, low power requirements, high noise immunity, high drive capability, an increased output voltage swing, reduced body effect, high current drivability and improved power dissipation comprises a CMOS inverter for receiving an input signal and bipolar push-pull output transistors (58, 59) for supplying an output. An intermediate CMOS stage (41, 42) is coupled between the CMOS inverter and the bipolar push-pull output transistors and to power supply voltages in a manner that eliminates body effect.

10. 发明申请

WO1985002955A1 TRANSIENT ACTIVE PULL-DOWN 审中-公开
标题翻译：瞬态主动上拉
公开(公告)号：WO1985002955A1
公开(公告)日：1985-07-04
申请号：PCT/US1984001711
申请日：1984-10-22
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , ALLEN, Michael
IPC分类号： H03K19/086
CPC分类号： H03K19/0136
摘要： An output voltage driver apparatus for an ECL circuit driving a capacitive load (CL) which comprises an emitter follower means (117) having an output emitter (118) and a reference emitter (120). The output emitter is connected to the capacitive load. A pull-down transistor means (123) is connected to the output emitter and provides a transient pull-down current for a capacitive load when the output voltage swings from a high level to a low level. A biasing means (125) is connected between the reference emitter of the emitter follower means and the pull-down transistor means so that the pull-down transistor means is biased to turn on when the voltage at the output emitter is higher than the voltage at the reference emitter by a turn-on voltage. Because the capacitive load will hold the voltage of the output emitter higher than that of the reference emitter until the capacitance of the load is discharged, the pull-down transistor means provides a transient pull-down current which speeds up the switching time of the emitter couple logic circuit.

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