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1. 发明申请

WO2017204902A1 PHASE CONTINUITY TECHNIQUE FOR FREQUENCY SYNTHESIS 审中-公开
标题翻译：用于频率综合的相位连续技术
公开(公告)号：WO2017204902A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/025547
申请日：2017-03-31
申请人： QUALCOMM INCORPORATED
发明人： ZANUSO, Marco , ELBADRY, Mohammad , HUNG, Tsai-Pi , SRIDHARA, Ravi , GATTA, Francesco , ZHUANG, Jingcheng
IPC分类号： H03L7/14
CPC分类号： H04L7/033 , H03L7/14 , H03L7/143 , H03L7/1976 , H03L2207/08 , H04L5/14 , H04L69/28 , H04W84/042
摘要： A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
摘要翻译：相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。当第一个锁相环打开时，此实现可保持相位连续性。

2. 发明申请

WO0019641A9 APPARATUS FOR LOW POWER RADIO COMMUNICATIONS 审中-公开
标题翻译：低功耗无线电通信设备
公开(公告)号：WO0019641A9
公开(公告)日：2000-09-28
申请号：PCT/US9814387
申请日：1998-07-21
申请人： CLEVELAND MED DEVICES INC , DACUS FARRON L , SCHMIDT ROBERT N , HENDRIX STEVEN P
发明人： DACUS FARRON L , SCHMIDT ROBERT N , HENDRIX STEVEN P
IPC分类号： H03C3/09 , H03J7/04 , H03L7/08 , H03L7/14 , H04B1/16 , H04B7/26
CPC分类号： H03C3/0958 , H03C3/095 , H03J7/04 , H03L7/0802 , H03L7/14 , H04W52/028 , Y02D70/00
摘要： A low-power radio transceiver comprising a loop filter/sample and hold circuit (66) for storing the VCO (32), control voltage (40), thereby allowing the PLL in the synthesizer (2), to be opened and closed with minimum output frequency drift. Power consumption is reduced by partially powering down the synthesizer (2) during open-loop operation. Automatic frequency control is provided in the receiver.
摘要翻译：一种低功率无线电收发器，包括用于存储VCO（32）的环路滤波器/采样和保持电路（66），控制电压（40），从而允许合成器（2）中的PLL以最小的速率被打开和关闭输出频率漂移。在开环操作期间通过部分关闭合成器（2）来降低功耗。在接收机中提供自动频率控制。

3. 发明申请

WO00038324A1 PLL AND GAIN CONTROL FOR CLOCK RECOVERY 审中-公开
标题翻译： PLL和增益控制用于时钟恢复
公开(公告)号：WO00038324A1
公开(公告)日：2000-06-29
申请号：PCT/US1999/030205
申请日：1999-12-17
IPC分类号： H03L7/085 , H03L7/087 , H03L7/093 , H03L7/14 , H04L7/033
CPC分类号： H03L7/14 , H03L7/085 , H03L7/087 , H03L7/093 , H04L7/033
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit (200). A fine loop of the PLL includes a phase detector (204) providing a differential analog voltage output. Transconductance circuitry (210) converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which can be controlled by an automatic gain adjust circuit (260, 270). A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator (212).
摘要翻译：高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。接收器电路具有双锁相环（PLL）电路（200）。 PLL的精细环路包括提供差分模拟电压输出的相位检测器（204）。跨导电路（210）将差分模拟电压输出转换为低电流模拟输出。跨导电路具有可由增益调节电路（260,270）控制的可变增益。 PLL的粗略回路允许快速采集内部振荡器（212）。

4. 发明申请

WO1997019513A1 DYNAMIC PHASE SELECTOR PHASE LOCKED LOOP CIRCUIT 审中-公开
标题翻译：动态相位选择器相位锁定环路
公开(公告)号：WO1997019513A1
公开(公告)日：1997-05-29
申请号：PCT/US1996018302
申请日：1996-11-15
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , KOVACS, Janos , KROESEN, Ronald , McCALL, Kevin
IPC分类号： H03D03/24
CPC分类号： H03K3/0231 , H03K3/03 , H03K3/0322 , H03L7/081 , H03L7/087 , H03L7/0996 , H03L7/14
摘要： A dynamic phase selector phase locked loop circuit (20) includes: an A/D converter (24) for receiving an input signal (22) to be sampled; a phase detection circuit (26) for determining the phase error between the input signal (22) and a clock signal; a clock circuit (30), responsive to the phase detection circuit (26), for providing the clock signal to the A/D converter for timing the sampling of the input signal (22); the clock circuit (30) including a delay circuit having a number of delay taps; and a phase selector circuit (42), responsive to the phase detection circuit (26) for initially gating (43) the clock signals to the A/D converter from the clock circuit (30), and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.
摘要翻译：动态相位选择器锁相环电路（20）包括：A / D转换器（24），用于接收待采样的输入信号（22）; 相位检测电路（26），用于确定输入信号（22）和时钟信号之间的相位误差; 响应于相位检测电路（26）的时钟电路（30），用于将时钟信号提供给A / D转换器，以对输入信号（22）的采样进行定时; 所述时钟电路（30）包括具有多个延迟抽头的延迟电路; 以及相位选择器电路（42），响应于所述相位检测电路（26），用于从时钟电路（30）首先将所述时钟信号选通（43）到所述A / D转换器，以及使所述延迟抽头之一动态地调整时钟信号的相位并减少初始相位误差。

5. 发明申请

WO1996017435A1 STEERED FREQUENCY PHASE LOCKED LOOP 审中-公开
标题翻译：转向频率相位锁定环
公开(公告)号：WO1996017435A1
公开(公告)日：1996-06-06
申请号：PCT/AU1995000793
申请日：1995-11-28
申请人： CURTIN UNIVERSITY OF TECHNOLOGY , HILL, Martin
发明人： CURTIN UNIVERSITY OF TECHNOLOGY
IPC分类号： H03L07/07
CPC分类号： H03L7/14 , H03L7/087 , H04L7/033
摘要： A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCO) (20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency ( omega 'r). Applications of the SFPLL include demodulation in CW modulation systems and timing recovery from NRZ data. Three advantages of the SFPLL are that the output frequency is equal or close to the reference frequency when no input signal is present, and the range of frequencies to which the SFPLL can lock is confined to a region around the reference frequency, and the phase and frequency instabilities of the VCO can be reduced.
摘要翻译：转向频率锁相环（SFPLL）包括一个相位循环，其功能类似于正常的锁相环（PLL）并锁定到输入信号，以及一个使用参考频率影响相位回路并有效地限制输出的频率回路相位环的频率和SFPLL在接近基准频率的频率范围内。选择参考频率非常接近SFPLL锁定到的输入信号频率。 SFPLL包括相位检测器（10），频率检测器（22），第一和第二增益分量（12,24），第一，第二和第三滤波器组件（14,18,26），夏季（16）和压控振荡器（VCO）（20）。通过明智地选择相位和频率环路的增益，可以设计SFPLL，使得SFPLL锁定的频率范围可以被限制在参考频率（ω'r）周围的任意小的区域。 SFPLL的应用包括CW调制系统中的解调和NRZ数据的定时恢复。 SFPLL的三个优点是当没有输入信号时，输出频率等于或接近参考频率，SFPLL可以锁定的频率范围限制在参考频率周围的一个区域，而相位和可以降低VCO的频率不稳定性。

6. 发明申请

WO1995009485A1 METHOD FOR CONTROLLING A PHASE-LOCKED LOOP, AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：用于控制相位锁定环路的方法和相位锁定环路
公开(公告)号：WO1995009485A1
公开(公告)日：1995-04-06
申请号：PCT/FI1994000432
申请日：1994-09-26
申请人： NOKIA TELECOMMUNICATIONS OY , KIVIJÄRVI, Antti
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03L07/14
CPC分类号： H03L7/199 , H03L7/081 , H03L7/14 , H03L7/145
摘要： The invention relates to a method for controlling a phase-locked loop in a locking situation, and to a phase-locked loop. The loop comprises a phase detector (13), a loop filter (14) and a voltage-controlled oscillator (15) connected in succession, a feedback path being established from the output of the oscillator to a second input (12) in the phase detector. In response to a change causing a currently used input signal to become inadequate for locking, the signal connected from the loop filter (14) to the oscillator (15) is frozen to a constant value, and in response to a change causing a currently used signal to become again adequate for locking, the freezing is removed. In the method, in order that the locking would take place directly, without any sudden phase changes, (a) the output signal of the loop filter (14) is additionally maintained substantially at said constant value by means of the feedback loop (25; 45) in response to a change causing the currently used input signal to become inadequate for locking; and (b) the control provided by said feedback loop for the loop filter (14) is frozen substantially at its current value in response to a change causing the signal to become again adequate for locking.
摘要翻译：本发明涉及一种用于在锁定情况下控制锁相环的方法以及锁相环。环路包括相位检测器（13），环路滤波器（14）和压控振荡器（15），反相路径从振荡器的输出到相位的第二输入端（12）被建立探测器。响应于导致当前使用的输入信号变得不适于锁定的变化，从环路滤波器（14）连接到振荡器（15）的信号被冻结到恒定值，并且响应于导致当前使用的信号变得再次足够锁定，冻结被去除。在该方法中，为了直接进行锁定，没有任何突然的相位变化，（a）环路滤波器（14）的输出信号通过反馈回路（25; 25）被额外维持在所述恒定值。 45）响应于导致当前使用的输入信号变得不适于锁定的变化; 并且（b）由环路滤波器（14）的所述反馈回路提供的控制响应于导致信号变得再次适合于锁定的变化被大致冻结在其当前值。

7. 发明申请

WO1994024768A1 A PHASE LOCK LOOP WITH ERROR CONSISTENCY DETECTOR 审中-公开
标题翻译：具有错误一致性检测器的相位锁定环
公开(公告)号：WO1994024768A1
公开(公告)日：1994-10-27
申请号：PCT/US1994004291
申请日：1994-04-19
申请人： RCA THOMSON LICENSING CORPORATION , SAUER, Donald, Jon , RODDA, William , CAMPBELL, Edward, Richard, III , DELL'OVA, Francis
发明人： RCA THOMSON LICENSING CORPORATION
IPC分类号： H03L07/113
CPC分类号： H03B5/24 , H03B5/20 , H03B2200/0038 , H03B2200/005 , H03B2200/0058 , H03B2201/02 , H03B2201/025 , H03B2201/0266 , H03J2200/10 , H03L7/099 , H03L7/0991 , H03L7/113 , H03L7/14 , H04N5/126 , H04N7/122
摘要： A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected an the phase-lock-loop circuit operates in an idle mode of operation.
摘要翻译：锁相环电路的相位检测器测量振荡器的输出信号与同步信号之间的相位误差。当在一对水平行周期内测量的相位误差之间的差异超过相位误差不一致的第一幅度时，相位锁定回路电路的运行不会纠正振荡器输出信号的相位空闲操作模式。

8. 发明申请

WO1994024767A1 AN OSCILLATOR WITH SWITCHED REACTIVE ELEMENTS 审中-公开
标题翻译：具有开关反应元件的振荡器
公开(公告)号：WO1994024767A1
公开(公告)日：1994-10-27
申请号：PCT/US1994004404
申请日：1994-04-19
申请人： RCA THOMSON LICENSING CORPORATION , SAUER, Donald, Jon , RODDA, William , CAMPBELL, Edward, Richard, III
发明人： RCA THOMSON LICENSING CORPORATION
IPC分类号： H03L07/099
CPC分类号： H03B5/24 , H03B5/20 , H03B2200/0038 , H03B2200/005 , H03B2200/0058 , H03B2201/02 , H03B2201/025 , H03B2201/0266 , H03J2200/10 , H03L7/099 , H03L7/0991 , H03L7/113 , H03L7/14 , H04N5/126 , H04N7/122
摘要： A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.
摘要翻译：锁相环电路包括具有开关电容器的振荡器，其以粗频率误差校正操作模式选择性地耦合到振荡器的正反馈路径。当频率误差小时，电路在精细的纠错模式下工作，而不改变切换的无功元件的选择。

9. 发明申请

WO1983001120A1 DOPPLER DROPOUT COMPENSATING SIGNAL CONDITIONING CIRCUIT 审中-公开
标题翻译：多普勒压差信号调理电路
公开(公告)号：WO1983001120A1
公开(公告)日：1983-03-31
申请号：PCT/US1981001300
申请日：1981-09-24
申请人： CATERPILLAR TRACTOR CO. , RIEBSCHLAGER, Jeffrey, J.
发明人： CATERPILLAR TRACTOR CO.
IPC分类号： G01S13/58
CPC分类号： H03L7/14 , G01S13/586
摘要： A dropout compensating signal conditioning circuit (10) especially well suited for conditioning signals utilized in doppler shift monitoring apparatus. The circuit (10) includes phase-locked loop (32) responsive to an input signal at (30) for generating a second signal at (44) of a frequency substantially directly proportional to the input signal. This circuit (10) provides an output on line (75) which tracks the input at (12) with great precision and is free from the occasional absence of one or more periods of the input signals, which is known as dropout.
摘要翻译：一种压差补偿信号调节电路（10），特别适用于在多普勒频移监测装置中使用的调理信号。电路（10）包括响应于（30）处的输入信号的锁相环（32），用于在（44）处产生与输入信号基本成正比的频率的第二信号。该电路（10）提供在线（75）上的输出，其以非常精确的方式跟踪（12）的输入，并且不存在输入信号的一个或多个周期，这被称为退出。

10. 发明申请

WO2013112763A1 DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 审中-公开
标题翻译：双模式时钟/数据恢复电路
公开(公告)号：WO2013112763A1
公开(公告)日：2013-08-01
申请号：PCT/US2013/023025
申请日：2013-01-24
申请人： QUALCOMM INCORPORATED
发明人： ZHUANG, Jingcheng , DANG, Nam, V. , KONG, Xiaohua , ZHU, Zhi , SOWLATI, Tirdad , AMELIFARD, Behnam
IPC分类号： H03L7/08 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/033
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间将锁定保持在串行数据突发的相位上。

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