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1. 发明申请

WO01047109A2 LOW VOLTAGE DIFFERENTIAL SIGNAL (LVDS) INPUT CIRCUIT 审中-公开
标题翻译：低电压差分信号（LVDS）输入电路
公开(公告)号：WO01047109A2
公开(公告)日：2001-06-28
申请号：PCT/EP2000/012508
申请日：2000-12-11
IPC分类号： H03F3/45 , H03K5/24 , H04L25/02 , H03K
CPC分类号： H04L25/0292 , H03F3/45085 , H03F3/45556 , H03F3/4556 , H03F2203/45418 , H03F2203/45424 , H03F2203/45592 , H03K5/2418 , H04L25/0276 , H04L25/028
摘要： Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits (3 and 5), respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) (1) is applied across a pair of series connected resistors (7 and 9), and to the inputs of the amplifiers (3 and 5). The common mode voltage signal (11) is fed to the inputs of third and fourth amplifiers (15 and 17). The third and fourth amplifiers (15 and 17) ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.
摘要翻译：使用分别在第一和第二电压子范围内工作的第一和第二放大器电路（3和5）来解决在宽共模电压范围内使用双极性差分电路相关的问题。低电压差分信号（LVDS）（1）被施加在一对串联连接的电阻（7和9）和放大器（3和5）的输入端。共模电压信号（11）被馈送到第三和第四放大器（15和17）的输入端。第三和第四放大器（15和17）确保LVDS接收器在差分输入信号范围和整个共模范围内具有恒定的线性传输特性，特别是在放大器过渡区域。

2. 发明申请

WO2016161277A1 BALANCED DIFFERENTIAL TRANSIMPEDANCE AMPLIFIER WITH SINGLE ENDED INPUT AND BALANCING METHOD 审中-公开
标题翻译：具有单端输入和平衡方法的平衡差分放大器
公开(公告)号：WO2016161277A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/025542
申请日：2016-04-01
申请人： TYCO ELECTRONICS CORPORATION
发明人： SMITH, Robert, Monroe , MCCLAY, Charles Phillip
IPC分类号： H03F1/08 , H03F3/08 , H03F3/45
CPC分类号： H03F1/56 , H03F1/0205 , H03F1/083 , H03F3/08 , H03F3/45076 , H03F3/45085 , H03F3/45183 , H03F3/45475 , H03F3/45605 , H03F3/45609 , H03F3/45618 , H03F3/45753 , H03F3/45757 , H03F3/45766 , H03F3/45977 , H03F3/45982 , H03F3/45991 , H03F2200/135 , H03F2200/18 , H03F2200/222 , H03F2200/228 , H03F2200/36 , H03F2200/393 , H03F2200/453 , H03F2200/456 , H03F2200/462 , H03F2200/471 , H03F2200/474 , H03F2200/72 , H03F2200/75 , H03F2203/45036 , H03F2203/45051 , H03F2203/45114 , H03F2203/45116 , H03F2203/45138 , H03F2203/45146 , H03F2203/45152 , H03F2203/45154 , H03F2203/45166 , H03F2203/45202 , H03F2203/45208 , H03F2203/45221 , H03F2203/45276 , H03F2203/45336 , H03F2203/45374 , H03F2203/45398 , H03F2203/45528 , H03F2203/45541 , H03F2203/45556 , H03F2203/45564 , H03F2203/45566 , H03F2203/45592 , H03F2203/45594 , H03F2203/45652 , H03F2203/45682 , H03F2203/45702
摘要： A balanced differential transimpedance amplifier with a single-ended input operational over a wide variation in the dynamic range of input signals. A threshold circuit is employed to either or a combination of (1) generate a varying decision threshold to ensure a proper slicing over a wide range of input current signal levels; and (2) generate a bias current and voltage applied to an input of a transimpedance stage to cancel out a dependence of the transimpedance stage voltage input on input current signal levels.
摘要翻译：平衡差分跨阻放大器，具有单端输入，可在输入信号的动态范围内进行广泛的变化。阈值电路被采用或（或）组合（1）产生变化的判定阈值以确保在宽范围的输入电流信号电平上的适当的分片; 并且（2）产生施加到跨阻抗级的输入的偏置电流和电压，以消除跨导级电压输入对输入电流信号电平的依赖性。

3. 发明申请

WO2013150156A1 EXTREMELY HIGH FREQUENCY DUAL-MODE CLASS AB POWER AMPLIFIER 审中-公开
标题翻译：极高频双模AB功率放大器
公开(公告)号：WO2013150156A1
公开(公告)日：2013-10-10
申请号：PCT/EP2013/057259
申请日：2013-04-05
申请人： ST-ERICSSON SA
发明人： DIETER, Joos , PHILIBERT, Wim , REYNAERT, Patrick , ZHAO, Dixian
IPC分类号： H03F3/195 , H03H7/48 , H03F1/02
CPC分类号： H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/213 , H03F3/72 , H03F2200/06 , H03F2200/09 , H03F2200/222 , H03F2200/312 , H03F2200/396 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/421 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/72 , H03F2200/75 , H03F2203/21106 , H03F2203/21142 , H03F2203/21175 , H03F2203/45018 , H03F2203/45036 , H03F2203/45172 , H03F2203/45206 , H03F2203/45556 , H03F2203/45566 , H03F2203/45592 , H03F2203/45621 , H03F2203/45638 , H03F2203/45726 , H03F2203/45728 , H03F2203/45731 , H03F2203/7221 , H03F2203/7224 , H03H7/48
摘要： An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.
摘要翻译：具有功率组合器的极高频（EHF）双模PA采用40-nm大容量CMOS技术设计。对于低功率应用，其中一个单元PA可以关闭。在设计中，执行电路级优化和权衡，以确保两种模式的良好性能。 PA实现了17.4dBm的PSAT，在高功率模式下具有29.3％的PAE，在低功率模式下，PAAT为12.6dBm，PAE为19.6％。还进行可靠性测量，并且基于常用的经验模型估计80613小时的寿命。在该设计中实现的优异性能（例如，最高报告的PAE）进一步证实了CMOS技术的缩放将继续有利于mm波收发器设计。

4. 发明申请

WO2006062941A2 AMPLIFIER SYSTEM WITH CURRENT-MODE SERVO FEEDBACK 审中-公开
标题翻译：具有电流模式伺服反馈的放大器系统
公开(公告)号：WO2006062941A2
公开(公告)日：2006-06-15
申请号：PCT/US2005044059
申请日：2005-12-07
申请人： WORLD ENERGY LABS 2 INC , LALETIN WILLIAM H
发明人： LALETIN WILLIAM H
IPC分类号： H03F3/45 , G01R31/36
CPC分类号： H03F3/45479 , G01R31/3004 , G01R31/31706 , G01R31/31716 , G01R31/3631 , H03F1/34 , H03F3/211 , H03F3/45475 , H03F3/45968 , H03F2200/261 , H03F2200/91 , H03F2203/45138 , H03F2203/45212 , H03F2203/45521 , H03F2203/45592
摘要： A system and method for compensating an amplifier apparatus for low frequency and/or DC components of an externally applied input signal as well as for any voltage offsets contributed by the amplifier circuitry. Band-limited servo feedback is applied to predetermined nodes in the forward gain path to null out unwanted signal components, leaving a residual signal that, when amplified, will be centered around ground, so that the full dynamic range of the amplifier system may be utilized. Consequently, the signal-to-noise ratio available at the output of the amplifier system will be maximized. The servo compensation may either operate in continuous time, or it may be held constant once a suitable level of compensation has been established, or it may be adjusted from time to time to accommodate slow variations of the average DC component of the input signal.
摘要翻译：一种用于补偿放大器装置的系统和方法，用于外部施加的输入信号的低频和/或直流分量以及由放大器电路提供的任何电压偏移。将带限伺服反馈应用于正向增益路径中的预定节点以消除不想要的信号分量，留下残余信号，该信号在被放大时将以地为中心，从而可以利用放大器系统的全动态范围。因此，放大器系统输出端的信噪比将最大化。伺服补偿可以连续运行，也可以在建立合适的补偿电平后保持不变，或者可以随时进行调整，以适应输入信号平均直流分量的缓慢变化。

5. 发明申请

WO2005124997A1 CURRENT-MODE INSTRUMENTATION AMPLIFIER 审中-公开
标题翻译：电流模式放大器
公开(公告)号：WO2005124997A1
公开(公告)日：2005-12-29
申请号：PCT/US2005/021250
申请日：2005-06-15
申请人： ANALOG DEVICES, INC.
发明人： BOTKER, Thomas, L.
IPC分类号： H03F3/30
CPC分类号： H03F1/086 , G05F3/262 , H03F3/217 , H03F3/38 , H03F3/393 , H03F3/45179 , H03F3/45273 , H03F3/45744 , H03F2200/261 , H03F2200/91 , H03F2203/45592
摘要： A current-mode instrumentation amplifier (IA) includes first and second buffer amplifiers which receive a differential voltage (VINP-VINN) and provide output voltages at respective output nodes; a resistance Rl is connected between the nodes and conducts a current I R1 that varies with VINP-VINN. In one embodiment, each amplifier includes a transistor connected in series with Ri which conducts current I R1 ; these currents are coupled to the input and output terminals of a current mirror, preferably via respective virtual ground nodes such that the IA requires only one current mirror, to produce the IA's output voltage. To minimize DC mismatch errors, the IA is chopper-stabilized, with the buffer amplifiers and signal current paths chopped using a two-phase chopping cycle.
摘要翻译：电流模式仪表放大器（IA）包括接收差分电压（VINP-VINN）并在相应输出节点处提供输出电压的第一和第二缓冲放大器; 电阻R1连接在节点之间并传导随VINP-VINN变化的电流IR1。在一个实施例中，每个放大器包括与Ri串联的晶体管，其导通电流IR1; 这些电流优选地经由相应的虚拟接地节点耦合到电流镜的输入和输出端子，使得IA仅需要一个电流镜来产生IA的输出电压。为了最小化DC失配误差，IA被斩波稳定，缓冲放大器和信号电流路径使用两相斩波周期斩波。

6. 发明申请

WO2014203525A1 増幅回路及び増幅回路ＩＣチップ审中-公开
标题翻译：放大器电路和放大器电路芯片
公开(公告)号：WO2014203525A1
公开(公告)日：2014-12-24
申请号：PCT/JP2014/003258
申请日：2014-06-17
申请人：旭化成エレクトロニクス株式会社
发明人：小川　智彦 , 小泉　佳彦
IPC分类号： H03F3/34 , G01P3/44 , G01P15/12
CPC分类号： H03F1/56 , G01P3/44 , G01P3/487 , G01P15/12 , G01P15/123 , G01R27/02 , H03F3/45071 , H03F3/45475 , H03F3/45932 , H03F2200/261 , H03F2200/294 , H03F2200/504 , H03F2200/555 , H03F2203/45138 , H03F2203/45336 , H03F2203/45528 , H03F2203/45591 , H03F2203/45592
摘要：　本発明は、ノイズ成分を低減して高ＳＮ比や低ノイズかつ小面積となる増幅回路及び増幅回路ＩＣチップに関する。増幅回路（１００）は、所定の物理量を抵抗値に変換する変換部（７０）を備え、変換部（７０）により変換された抵抗値を電圧値に変換して増幅するように構成される。変換部（７０）は、ピエゾ抵抗素子からなる可変抵抗型センサ（７１，７２）を備える。バイアス部（８０）は、変換部（７０）のバイアス電流を決定するもので、バイアス抵抗（８１，８２）を備える。演算増幅部（９０）は、バイアス部（８０）と変換部（７０）に基づく出力信号を入力信号とし、第１の演算増幅器（１０１）の入出力端に接続されるフィードバック抵抗（９１，９２）を備え、第１の演算増幅器（１０１）は、コモンモードフィードバック回路を備えた全差動演算増幅器である。
摘要翻译：本发明涉及一种降低噪声分量的低噪声，小尺寸因子放大器电路和放大器电路芯片，产生较高的信噪比。设置有将规定物理量转换为电阻值的转换单元（70）的所述放大电路（100）被设计为将来自转换单元（70）的电阻值转换为电压值并放大相同。转换单元（70）设置有包括压阻元件的可变电阻传感器（71,72）。确定流经转换单元（70）的偏置电流的偏置单元（80）设置有偏置电阻（81,82）。使用基于偏置单元（80）和转换单元（70）的输出信号作为运算放大器单元（90）的输入信号，该运算放大器单元设置有连接到输入端的反馈电阻（91,92）第一运算放大器（101）的输出端子。所述第一运算放大器（101）是具有共模反馈电路的全差分运算放大器。

7. 发明申请

WO0193491A3 HIGH FREQUENCY NETWORK TRANSMITTER 审中-公开
标题翻译：高频网络发射机
公开(公告)号：WO0193491A3
公开(公告)日：2003-09-04
申请号：PCT/US0118031
申请日：2001-06-04
申请人： CONNECTCOM MICROSYSTEMS INC
发明人： ENAM SYED KHURSHEED
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05 , H03K19/0175 , H03L7/00 , H03M9/00 , H04L7/02
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： A high frequency network transmitter receives a parallel input data stream and serializes the parallel input data stream for high speed transmission in a network. A phase alignment circuit aligns the parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock. A phase frequency detector in a clock multiply unit of the transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. A voltage controlled oscillator in the clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. A high-speed output driver produces a fast differential output signal for the serial transmitter. The output driver includes a first stage circuit which comprises a first active element to pull the first stage circuit output to a logic high and a second active element to pull the first stage circuit output to a logic low. The first stage circuit drives a second stage circuit which reacts relatively quickly to signal transitions by steering substantially constant current between differential pair transistors.
摘要翻译：高频网络发射机接收并行输入数据流，并串行化并行输入数据流，以在网络中进行高速传输。在使用第二传输时钟转换为串行输出数据流之前，相位对准电路将并行输入数据流对准第一传输时钟。发射机的时钟乘法单元中的相位频率检测器检测参考时钟和由时钟乘法单元产生的内部时钟之间的相位和频率差异。相位频率检测器包括复位电路，其增加了相位频率检测器的灵敏度和可靠性，从而允许相位频率检测器以高速运行。时钟倍增单元中的压控振荡器包括由多个相应的控制电压信号控制的多个变容二极管。多个变容二极管允许组合有效的方法来设置压控振荡器的输出信号频率。高速输出驱动器为串行发送器产生快速差分输出信号。输出驱动器包括第一级电路，其包括将第一级电路输出拉至逻辑高电平的第一有源元件和将第一级电路输出拉至逻辑低的第二有源元件。第一级电路驱动第二级电路，其通过在差分对晶体管之间转向基本恒定的电流来相对较快地对信号转换作出反应。

8. 发明申请

WO0195552A3 HIGH FREQUENCY NETWORK RECEIVER 审中-公开
标题翻译：高频网络接收器
公开(公告)号：WO0195552A3
公开(公告)日：2003-07-17
申请号：PCT/US0117962
申请日：2001-06-04
申请人： CONNECTCOM MICROSYSTEMS INC
发明人： ENAM SYED KYURSHEED
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05 , H03D13/00
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that allow a comparison of phase between a clock signal (326) and a serial bitstream (320). A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream (320) in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop (306). The phase-locked loop (306) can generate partially demultiplexed data (324), which is provided as an input to a demultiplexer (310). A framer circuit (312) searches demultiplexed data (328) for frame patterns and aligns the demultiplexed data (328). An acquisition aid circuit (308) indicates whether the clock signal (326) and a reference clock signal (332) are within a predetermined range.
摘要翻译：本发明涉及允许比较时钟信号（326）和串行比特流（320）之间的相位的方法和装置。相位检测器在相对固定的窗口中将串行位流（320）的相邻位或连续位之间的转换的一部分进行积分。有利地，相对固定的窗口允许在相对较高的频率（例如以SONET的OC-192速率）进行操作。整合结果包含在一个逻辑状态下花费在窗口内的时间量。整合结果保持到确定集成位的逻辑电平为止。逻辑电平转换的指示用于将积分结果与集成窗口内的转换时序联系起来。可以集成多个位转换，与定时信息相关，相加并作为输入提供给例如锁相环（306）中的压控振荡器。锁相环（306）可以产生部分解复用的数据（324），其作为输入提供给解复用器（310）。成帧器电路（312）搜索用于帧模式的解复用数据（328）并对准解复用数据（328）。获取辅助电路（308）指示时钟信号（326）和参考时钟信号（332）是否在预定范围内。

9. 发明申请

WO01095552A2 HIGH FREQUENCY NETWORK RECEIVER 审中-公开
标题翻译：高频网络接收器
公开(公告)号：WO01095552A2
公开(公告)日：2001-12-13
申请号：PCT/US2001/017962
申请日：2001-06-04
IPC分类号： H03D7/14 , H03H11/52 , H03K19/018 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H04J3/06 , H04L1/24 , H04L7/00 , H04L7/033 , H04L25/02 , H04L25/05
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that allow a comparison of phase between a clock signal (326) and a serial bitstream (320). A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream (320) in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop (306). The phase-locked loop (306) can generate partially demultiplexed data (324), which is provided as an input to a demultiplexer (310). A framer circuit (312) searches demultiplexed data (328) for frame patterns and aligns the demultiplexed data (328). An acquisition aid circuit (308) indicates whether the clock signal (326) and a reference clock signal (332) are within a predetermined range.
摘要翻译：本发明涉及允许比较时钟信号（326）和串行比特流（320）之间的相位的方法和装置。相位检测器在相对固定的窗口中将串行位流（320）的相邻位或连续位之间的转换的一部分进行积分。有利地，相对固定的窗口允许在相对较高的频率（例如以SONET的OC-192速率）进行操作。整合结果包含在一个逻辑状态下花费在窗口内的时间量。整合结果保持到确定集成位的逻辑电平为止。逻辑电平转换的指示用于将积分结果与集成窗口内的转换时序联系起来。可以集成多个位转换，与定时信息相关，相加并作为输入提供给例如锁相环（306）中的压控振荡器。锁相环（306）可以产生部分解复用的数据（324），其作为输入提供给解复用器（310）。成帧器电路（312）搜索用于帧模式的解复用数据（328）并对准解复用数据（328）。获取辅助电路（308）指示时钟信号（326）和参考时钟信号（332）是否在预定范围内。

10. 发明申请

WO0147109A3 LOW VOLTAGE DIFFERENTIAL SIGNAL (LVDS) INPUT CIRCUIT 审中-公开
标题翻译：低压差分信号（LVDS）输入电路
公开(公告)号：WO0147109A3
公开(公告)日：2001-12-13
申请号：PCT/EP0012508
申请日：2000-12-11
申请人： ERICSSON TELEFON AB L M
发明人： BANGS JOAKIM , THOMPSON JOHN , FILIPPI RAYMOND
IPC分类号： H03F3/45 , H03K5/24 , H04L25/02
CPC分类号： H04L25/0292 , H03F3/45085 , H03F3/45556 , H03F3/4556 , H03F2203/45418 , H03F2203/45424 , H03F2203/45592 , H03K5/2418 , H04L25/0276 , H04L25/028
摘要： Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits (3 and 5), respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) (1) is applied across a pair of series connected resistors (7 and 9), and to the inputs of the amplifiers (3 and 5). The common mode voltage signal (11) is fed to the inputs of third and fourth amplifiers (15 and 17). The third and fourth amplifiers (15 and 17) ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.
摘要翻译：使用分别在第一和第二电压子范围上操作的第一和第二放大器电路（3和5）来解决与在宽共模电压范围上使用双极差分电路相关的问题。低压差分信号（LVDS）（1）施加在一对串联的电阻（7和9）上，以及放大器（3和5）的输入上。共模电压信号（11）被馈送到第三和第四放大器（15和17）的输入端。第三和第四放大器（15和17）确保LVDS接收器在差分输入信号范围上和整个共模范围上，特别是在放大器过渡区域上具有恒定的线性传输特性。

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