专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019036154A1 MULTI-MODE POWER TRAIN INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2019036154A1
公开(公告)日：2019-02-21
申请号：PCT/US2018/043024
申请日：2018-07-20
申请人： WITRICITY CORPORATION
发明人： DER, Lawrence , GUPTA, Sanjay
IPC分类号： H03K3/356 , H03K19/094 , H03K17/10 , G05F3/20 , H03K19/003 , H03K19/017
CPC分类号： H03K3/356182 , G05F3/205 , H03K3/35613 , H03K17/102 , H03K19/00315 , H03K19/01721 , H03K19/09429
摘要： A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit.

2. 发明申请

WO2018208436A1 DIGITAL-TO-ANALOG CONVERTER 审中-公开
公开(公告)号：WO2018208436A1
公开(公告)日：2018-11-15
申请号：PCT/US2018/027578
申请日：2018-04-13
申请人： QUALCOMM INCORPORATED
发明人： TSENG, Yi-Hung
IPC分类号： H03M1/06 , H03M1/74
CPC分类号： H03M1/0678 , G06F1/10 , H03K5/2481 , H03K19/00315 , H03K19/00361 , H03M1/00 , H03M1/742 , H03M1/745 , H03M1/747
摘要： Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.

3. 发明申请

WO2017053090A1 INVERSELY PROPORTIONAL VOLTAGE-DELAY BUFFERS FOR BUFFERING DATA ACCORDING TO DATA VOLTAGE LEVELS 审中-公开
标题翻译：用于根据数据电压水平缓冲数据的反相电压延迟缓冲器
公开(公告)号：WO2017053090A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051073
申请日：2016-09-09
申请人： QUALCOMM INCORPORATED
发明人： PUCKETT, Joshua, Lance
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/003 , H03K19/00315 , H03K19/018507
摘要： Inversely proportional voltage-delay buffers (100) for buffering data (102) according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer (100) is configured to buffer a data signal (102) for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit (104) and pass circuit (106). The inversion circuit is configured to generate a control signal (108) that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit (106) is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.
摘要翻译：公开了用于根据数据电压电平缓冲数据（102）的相对成比例的电压 - 延迟缓冲器（100）。一方面，逆比例电压延迟缓冲器（100）被配置为缓冲与数据信号的电压电平成反比的时间量的数据信号（102）。逆比例电压延迟缓冲器包括反相电路（104）和通过电路（106）。反相电路被配置为产生作为数据信号的逻辑倒数的控制信号（108）。值得注意的是，控制信号以与数据信号的电压电平成比例的速率转变。通路电路（106）被配置为当数据信号和控制信号具有相同的逻辑状态时，产生数据信号的弱逻辑状态。通过电路被配置为当数据输入和控制信号具有相反的逻辑状态时，产生数据信号的强逻辑状态。

4. 发明申请

WO2017010637A1 3진수 논리회로 审中-公开
标题翻译： TERNARY数字逻辑电路
公开(公告)号：WO2017010637A1
公开(公告)日：2017-01-19
申请号：PCT/KR2015/014377
申请日：2015-12-29
申请人： 울산과학기술원
发明人： 김경록 , 신선해 , 장이산 , 정재원
IPC分类号： H03K19/20 , H03K19/0948
CPC分类号： G06F7/48 , G06F7/49 , H03K19/0016 , H03K19/00315 , H03K19/00361 , H03K19/09429 , H03K19/0948 , H03K19/20
摘要： 본 발명에 따른 3진수 논리회로는 전원전압 (V DD 와 GND) 사이에 직렬로 연결된 풀업 소자(100)와 풀다운 소자(200) 그리고 입력전압(V IN )과 출력전압(V OUT ) 을 포함하되, 상기 입력전압(V IN )에 의해 모두 꺼진 경우, 상기 풀업 소자(100)와 상기 풀다운 소자(200)가 모두 출력전압(V OUT )에만 영향을 받는 단순 저항으로 동작하며 전압 분배를 통해 제 3의 진수 ("1" 상태)를 형성하고, 상기 풀업 소자(100) 또는 풀다운 소자(200)의 한쪽만 켜져 전류를 흘려주게 되면 V DD ("2"상태) 또는 GND("0" 상태)가 출력전압(V OUT )으로 출력되도록 하여, bit density를 확연히 높일 수 있는 효과가 있다.
摘要翻译：根据本发明的三位数逻辑电路包括：在电源电压（VDD和GND）之间串联连接的上拉装置（100）和下拉装置（200）; 和输入电压（VIN）和输出电压（VOUT）。上拉装置（100）和下拉装置（200）均作为仅受输出电压（VOUT）影响的简单电阻器，并通过电压分配形成三进制数（“1”状态）当两个设备都被输入电压（VIN）关闭时。当只有一个上拉装置（100）和下拉装置（200）导通以允许电流流过其中时，VDD（“2”状态）或GND（“0”状态）被输出为输出电压（VOUT），以显着提高位密度。

5. 发明申请

WO2016167903A1 AUTOMATIC VOLTAGE SWITCHING CIRCUIT FOR SELECTING A HIGHER VOLTAGE OF MULTIPLE SUPPLY VOLTAGES TO PROVIDE AS AN OUTPUT VOLTAGE 审中-公开
标题翻译：用于选择更高电压的多电源供应电压作为输出电压的自动电压开关电路
公开(公告)号：WO2016167903A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/021655
申请日：2016-03-10
申请人： QUALCOMM INCORPORATED
发明人： PRICE, Burt, Lee , KOLLA, Yeshwant, Nagaraj , NATEKAR, Neel, Shashank
IPC分类号： H03K5/24 , H03K19/003 , H03K19/00
CPC分类号： H02J1/10 , H03K5/2481 , H03K19/0016 , H03K19/00315
摘要： Automatic voltage switching circuits for providing a higher voltage of multiple supply voltages are disclosed. In one aspect, an automatic voltage switching circuit (100) is configured to generate a compare signal (116) indicating which of a first supply voltage (104) and a second supply voltage (106) is a higher voltage. The automatic voltage switching circuit (100) is further configured to generate first and second select signals (122) based on the compare signal (116), wherein the first and second select signals (122) are in a voltage domain of the higher voltage. Transistors (124, 126) corresponding to the first and second supply voltages control switching the output voltage (102) to the higher voltage in response to the first and second select signals (122). Biasing the back-gates of the transistors using the output voltage (102) reduces or avoids forward biasing in the body diodes of the transistors (124, 126), thus reducing the possibility of the output voltage (102) causing interference on a power supply corresponding to a non-activated transistor.
摘要翻译：公开了用于提供更高电压的多电源电压的自动电压开关电路。一方面，自动电压切换电路（100）被配置为产生指示第一电源电压（104）和第二电源电压（106）中的哪一个是较高电压的比较信号（116）。自动电压切换电路（100）还被配置为基于比较信号（116）产生第一和第二选择信号（122），其中第一和第二选择信号（122）处于较高电压的电压域。对应于第一和第二电源电压的晶体管（124,126）响应于第一和第二选择信号（122）控制将输出电压（102）切换到更高的电压。使用输出电压（102）来偏置晶体管的背栅极减小或避免晶体管（124,126）的体二极管中的正向偏置，从而降低输出电压（102）对电源产生干扰的可能性对应于未激活的晶体管。

6. 发明申请

WO2016113468A1 A SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY 审中-公开
标题翻译：半导体逻辑元件和逻辑电路
公开(公告)号：WO2016113468A1
公开(公告)日：2016-07-21
申请号：PCT/FI2016/050014
申请日：2016-01-13
申请人： AUROLA, Artto Mikael
发明人： AUROLA, Artto Mikael
IPC分类号： H03K19/094 , H01L27/085 , H03K19/003 , H03K19/20 , H03K19/0952
CPC分类号： H03K19/20 , H01L27/0207 , H01L27/0629 , H01L27/092 , H01L27/098 , H01L27/1203 , H01L29/0692 , H01L29/7838 , H01L29/808 , H01L29/8083 , H03K19/0013 , H03K19/00315 , H03K19/094 , H03K19/0952
摘要： The invention relates to a semiconductor logic element comprising a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. The invention relates also to different kinds of logic circuitries comprising the described logic element.
摘要翻译：本发明涉及包括第一导电类型的场效应晶体管和第二导电类型的场效应晶体管的半导体逻辑元件。第一FET的栅极是半导体逻辑元件的输入，第二FET的漏极被称为半导体逻辑元件的输出，第二FET的源极是半导体逻辑元件的源极。通过将适用的电位施加到场效应晶体管的端子，可以影响逻辑元件的输出状态。本发明还涉及包括所描述的逻辑元件的不同种类的逻辑电路。

7. 发明申请

WO2015160452A2 HIGH-VOLTAGE INPUT RECEIVER USING LOW-VOLTAGE DEVICES 审中-公开
标题翻译：使用低电压设备的高压输入接收器
公开(公告)号：WO2015160452A2
公开(公告)日：2015-10-22
申请号：PCT/US2015/019958
申请日：2015-03-11
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K5/24
CPC分类号： H03K5/08 , H03K5/24 , H03K19/00315
摘要： An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.
摘要翻译：用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。降压装置将高电压域组合信号转换成降压低电压域信号。

8. 发明申请

WO2015069568A1 PSEUDO-DIFFERENTIAL INPUT CIRCUITRY WITH REFERENCE VOLTAGE 审中-公开
标题翻译：具有参考电压的PSEUDO差分输入电路
公开(公告)号：WO2015069568A1
公开(公告)日：2015-05-14
申请号：PCT/US2014/063502
申请日：2014-10-31
申请人： QUALCOMM INCORPORATED
发明人： HOLLIS, Timothy Mowry
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/018521 , H03K19/00315
摘要： System, methods and apparatus are described that facilitate data communications using a single-ended communication link. A method for data communications includes decoupling a direct current component from an alternating current component of a single-ended input signal, biasing the alternating current component with a predetermined bias voltage to obtain a realigned signal, and providing a digital output representative of the input signal by comparing the realigned signal with the predetermined bias voltage. The realigned signal can be compared with the predetermined bias voltage using hysteresis comparison to provide an output signal that switches between logic states compatible with a logic circuit.
摘要翻译：描述了使用单端通信链路促进数据通信的系统，方法和装置。一种用于数据通信的方法包括：将直流分量与单端输入信号的交流分量去耦，以预定偏置电压偏置交流分量，以获得重新对准的信号，以及提供代表输入信号的数字输出通过将重新排列的信号与预定的偏置电压进行比较。可以使用滞后比较将重新排列的信号与预定偏置电压进行比较，以提供在与逻辑电路兼容的逻辑状态之间切换的输出信号。

9. 发明申请

WO2013048727A3 MAINTAINING PULSE WIDTH MODULATION DATA-SET COHERENCY 审中-公开
标题翻译：维持脉冲宽度调制数据集合
公开(公告)号：WO2013048727A3
公开(公告)日：2013-05-23
申请号：PCT/US2012054734
申请日：2012-09-12
申请人： MICROCHIP TECH INC , KRIS BRYAN
发明人： KRIS BRYAN
IPC分类号： H03K7/08 , H02M3/156 , H03K19/003
CPC分类号： H03K7/08 , H02M3/1584 , H03K19/00315 , H04L25/4902
摘要： Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events, PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.
摘要翻译：生成多相，频率相干脉宽调制（PWM）信号，无论用户或系统事件如何，均可维持PWM数据集的一致性，通过在数据中添加数据缓冲器来保存和传输新的PWM数据来实现PWM数据集的一致性从处理器设置更新。在数据传输到数据缓冲区完成之后，当下一个PWM周期即将开始时，数据缓冲器中存储的数据组将及时传送到有源PWM寄存器，以便下一个PWM周期的开始。

10. 发明申请

WO2011130039A3 SIGNALING SYSTEMS, PREAMPLIFIERS, MEMORY DEVICES AND METHODS 审中-公开
标题翻译：信令系统，前置放大器，存储设备和方法
公开(公告)号：WO2011130039A3
公开(公告)日：2011-12-22
申请号：PCT/US2011031119
申请日：2011-04-04
申请人： MICRON TECHNOLOGY INC , LEE SEONG-HOON
发明人： LEE SEONG-HOON
IPC分类号： G11C7/10 , H03K19/0175
CPC分类号： H03F3/245 , H03K19/00315 , H04L25/0272
摘要： Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.
摘要翻译：公开了信号系统，前置放大器，存储设备和方法，例如包括被配置为接收第一数字信号的发射机的信号系统。发射机将对应于数字信号的发射信号提供给信号路径。耦合到信号线的接收机系统包括前置放大器，其被耦合以接收来自信号路径的传输信号。前置放大器包括配置成提供放大信号的共栅极放大晶体管。接收机系统还包括一个接收机，用于接收来自前置放大器的放大信号。接收器被配置为提供对应于由接收器接收的放大信号的第二数字信号。这样的信令系统可以用在存储器设备中或任何其他电子电路中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式