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1. 发明申请

WO2015081056A1 STATIC RANDOM ACCESS MEMORY (SRAM) GLOBAL BITLINE CIRCUITS FOR REDUCING POWER GLITCHES DURING MEMORY READ ACCESSES, AND RELATED METHODS AND SYSTEMS 审中-公开
标题翻译：静态随机访问存储器（SRAM）用于在存储器读取访问期间减少功率玻璃的全局位线电路及相关方法和系统
公开(公告)号：WO2015081056A1
公开(公告)日：2015-06-04
申请号：PCT/US2014/067269
申请日：2014-11-25
申请人： QUALCOMM INCORPORATED
发明人： PUCKETT, Joshua, Lance , LILES, Stephen, Edward , MARTZLOFF, Jason, Philip
IPC分类号： G11C7/18 , G11C11/419 , G11C7/10
CPC分类号： G11C11/419 , G11C7/1048 , G11C7/12 , G11C7/18
摘要： Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.
摘要翻译：公开了用于减少读访问期间的毛刺的静态随机存取存储器（SRAM）全局位线电路，以及相关的方法和系统。 SRAM中的全局位线方案可以减少输出负载，降低功耗。在某些实施例中，SRAM包括SRAM阵列。 SRAM包括用于每个SRAM阵列列的全局位线电路。每个全局位线电路包括对与SRAM阵列中的比特单元相对应的本地位线预充电的存储器访问电路。从所选位单元读取的数据从其本地位线读取到聚合读位线，即本地位线的聚合。 SRAM包括将聚合读取位线发送数据到全局位线的位线评估电路。基于时钟触发的上升转换发送数据而不是基于时钟触发的下降转换将数据发送到全局位线。可以使用全局位线方案，其减少毛刺并导致功率消耗的增加。

2. 发明申请

WO2017053090A1 INVERSELY PROPORTIONAL VOLTAGE-DELAY BUFFERS FOR BUFFERING DATA ACCORDING TO DATA VOLTAGE LEVELS 审中-公开
标题翻译：用于根据数据电压水平缓冲数据的反相电压延迟缓冲器
公开(公告)号：WO2017053090A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051073
申请日：2016-09-09
申请人： QUALCOMM INCORPORATED
发明人： PUCKETT, Joshua, Lance
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/003 , H03K19/00315 , H03K19/018507
摘要： Inversely proportional voltage-delay buffers (100) for buffering data (102) according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer (100) is configured to buffer a data signal (102) for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit (104) and pass circuit (106). The inversion circuit is configured to generate a control signal (108) that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit (106) is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.
摘要翻译：公开了用于根据数据电压电平缓冲数据（102）的相对成比例的电压 - 延迟缓冲器（100）。一方面，逆比例电压延迟缓冲器（100）被配置为缓冲与数据信号的电压电平成反比的时间量的数据信号（102）。逆比例电压延迟缓冲器包括反相电路（104）和通过电路（106）。反相电路被配置为产生作为数据信号的逻辑倒数的控制信号（108）。值得注意的是，控制信号以与数据信号的电压电平成比例的速率转变。通路电路（106）被配置为当数据信号和控制信号具有相同的逻辑状态时，产生数据信号的弱逻辑状态。通过电路被配置为当数据输入和控制信号具有相反的逻辑状态时，产生数据信号的强逻辑状态。

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