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1. 发明申请

WO2015078611A1 AMPLIFIER ARRANGEMENT 审中-公开
标题翻译：放大器布置
公开(公告)号：WO2015078611A1
公开(公告)日：2015-06-04
申请号：PCT/EP2014/070505
申请日：2014-09-25
申请人： AMS AG
发明人： FITZI, Andreas
IPC分类号： H03F1/26 , H03F3/45
CPC分类号： H03F1/26 , H03F3/21 , H03F3/45183 , H03F3/45237 , H03F3/45273 , H03F2203/45352 , H03F2203/45366
摘要： An amplifier arrangement is presented, comprising a first differential stage (DS1) comprising at least two transistors (M1, M1') having a first threshold voltage (Vth1), at least a second differential stage (DS2) comprising at least two transistors (M3, M3') having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage (DS1, DS2), respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor (M1) of the first differential stage and one transistor (M3) of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement.
摘要翻译：提供一种放大器装置，包括：第一差分级（DS1），包括具有第一阈值电压（Vth1）的至少两个晶体管（M1，M1'），至少包括至少两个晶体管的M3（M3），M3'）具有不同于第一阈值电压的第二阈值电压，第一和第二差分级（DS1，DS2）中的至少一个晶体管分别具有控制输入，该控制输入共同耦合到放大器装置的输入端，第一差分级的至少一个晶体管（M1）和第二差分级的一个晶体管（M3）被布置在公共电流路径中，该公共电流路径耦合到放大器装置的输出端。

2. 发明申请

WO2013015820A1 INDUCTIVE-ELEMENT FEEDBACK-LOOP COMPENSATOR 审中-公开
标题翻译：电感元件反馈环路补偿器
公开(公告)号：WO2013015820A1
公开(公告)日：2013-01-31
申请号：PCT/US2011/051678
申请日：2011-09-15
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , ADAMS, Douglas, Jay Kozak , SARPESHKAR, Rahul
发明人： ADAMS, Douglas, Jay Kozak , SARPESHKAR, Rahul
IPC分类号： H03F3/45 , H03F1/34
CPC分类号： H03F3/45085 , H03F1/083 , H03F1/34 , H03F2203/45296 , H03F2203/45298 , H03F2203/45316 , H03F2203/45352 , H03F2203/45374 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45554 , H03F2203/45594 , H03F2203/45702
摘要： Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.
摘要翻译：描述了耦合在运算放大器电路的差分输入之间的感应补偿网络。感应补偿网络包括至少一个感应元件，其具有选择的电感值，以便提供运算放大器电路的适当补偿。还描述了一种反馈补偿方案，其通过在反馈路径中添加电感或电容元件将零引入到系统中来调整环路特性。

3. 发明申请

WO2012085685A2 ACCURATE BIAS TRACKING FOR PROCESS VARIATION AND SUPPLY MODULATION 审中-公开
标题翻译：用于过程变化和供应调制的精确偏差跟踪
公开(公告)号：WO2012085685A2
公开(公告)日：2012-06-28
申请号：PCT/IB2011/003331
申请日：2011-12-20
申请人： MARVELL WORLD TRADE LTD. , LEONG, Poh, Boon , MANIAM, Nuntha, Kumar, Krisnasamy
发明人： LEONG, Poh, Boon , MANIAM, Nuntha, Kumar, Krisnasamy
CPC分类号： H03F3/16 , G05F3/262 , H03F3/193 , H03F3/245 , H03F3/45179 , H03F2200/555 , H03F2203/45294 , H03F2203/45301 , H03F2203/45304 , H03F2203/45311 , H03F2203/45352 , H03F2203/45544 , H03F2203/45554
摘要： A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
摘要翻译：电流镜包括偏置分支，偏置分支包括串联在电压源和地之间的第一和第二晶体管，耦合在电压源和地之间的分压器，被配置为接收分压器的分压的运算放大器和在第一和第二晶体管之间的节点的电压，并且驱动第二晶体管的栅极以将节点拉到分压。电流镜还包括耦合到偏压分支的功率放大器芯。功率放大器芯包括串联在电压源和地之间的第一和第二驱动晶体管。第一晶体管和第一驱动晶体管的栅极耦合，并且第二晶体管和第二驱动晶体管的栅极耦合。

4. 发明申请

WO2011099113A1 差動増幅回路审中-公开
标题翻译：差分放大器电路
公开(公告)号：WO2011099113A1
公开(公告)日：2011-08-18
申请号：PCT/JP2010/051849
申请日：2010-02-09
申请人：株式会社島津製作所 , 土生俊也
发明人：土生　俊也
IPC分类号： H03F3/45 , H03F3/19
CPC分类号： H03F3/45085 , H03F3/189 , H03F2200/451 , H03F2203/45352 , H03F2203/45371 , H03F2203/45466 , H03F2203/45468 , H03F2203/45496 , H03F2203/45498 , H03F2203/45702
摘要：　一対の入力段トランジスタ（１０、１２）のエミッタ端子と抵抗（１９、２０）との間にそれぞれ補償用トランジスタ（１７、１８）を挿入し、そのトランジスタ（１７、１８）のベース端子を互いに他方のトランジスタ（１７、１８）のコレクタ端子に接続する。この補償用トランジスタ（１７、１８）のベース－エミッタ間の電圧変化量により入力段トランジスタ（１０、１２）ベース－エミッタ間の電圧変化量の影響がキャンセルされるため、入力の差電圧Ｖ dif と出力電圧ΔＶ out との関係はトランジスタのエミッタ等価抵抗に依存せず、抵抗（１４－１６）の値にのみ依存する比例関係となる。これにより、従来のように入力段でトランジスタを複数並列接続する必要がなく、周波数特性を改善することができ、ゲインの精度、安定度も向上する。
摘要翻译：在一对输入级晶体管（10和12）和电阻器（19和20）的每个发射极端子之间分别插入补偿晶体管（17和18），并且晶体管（17和18）的每个基极相互相互连接到另一个晶体管（17或18）的集电极端子。输入级晶体管（10和12）的基极 - 发射极电压变化的影响被补偿晶体管（17和18）的基极 - 发射极电压的变化所抵消，因此，输入的差分电压Vdif与输出电压ΔV2的关系不依赖于晶体管的发射极的等效电阻，而仅取决于电阻器（14至16）的值。结果，现有技术中在输入级并联多个晶体管的需要不存在，因此可以改善频率特性，导致增益精度和可靠性程度的提高。

5. 发明申请

WO2010006220A1 INSTRUMENTATION INPUT SYSTEMS 审中-公开
标题翻译：仪器输入系统
公开(公告)号：WO2010006220A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/050179
申请日：2009-07-09
申请人： ANALOG DEVICES, INC. , GILBERT, Barrie
发明人： GILBERT, Barrie
IPC分类号： H03F3/217
CPC分类号： H03G3/004 , H03F1/302 , H03F1/52 , H03F3/211 , H03F3/4508 , H03F3/45089 , H03F3/45278 , H03F3/45282 , H03F3/45475 , H03F3/45497 , H03F3/45852 , H03F3/45937 , H03F3/45986 , H03F3/72 , H03F2200/165 , H03F2200/168 , H03F2200/261 , H03F2200/375 , H03F2200/405 , H03F2200/411 , H03F2203/45301 , H03F2203/45352 , H03F2203/45358 , H03F2203/45424 , H03F2203/45526 , H03F2203/45544 , H03F2203/45548 , H03F2203/45594 , H03F2203/45618 , H03F2203/45634 , H03F2203/45644 , H03F2203/45702 , H03F2203/45732 , H03G3/001
摘要： An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.
摘要翻译：用于仪器系统的输入级可以包括耦合在输入端和求和节点之间的电阻器，以及布置成保持加法节点处的电压的放大器。在另一个实施例中，仪器输入系统可以包括用于接收要测量的信号的输入级，以及具有耦合到输入级的输出的输入的可变增益放大器，其中可变增益放大器包括两个或更多个增益级。可变增益放大器可以包括具有输入和一系列抽头点的衰减器和一系列低惯量开关，用于将衰减器的输出转向输出端。

6. 发明申请

WO2009078112A1 演算増幅器，パイプライン型ＡＤ変換器审中-公开
标题翻译：算术放大器和管道式AD转换器
公开(公告)号：WO2009078112A1
公开(公告)日：2009-06-25
申请号：PCT/JP2008/002041
申请日：2008-07-30
申请人：パナソニック株式会社 , 野間崎大輔 , 岡浩二
发明人：野間崎大輔 , 岡浩二
IPC分类号： H03F3/45 , H01L21/82 , H01L21/822 , H01L27/04 , H03M1/14
CPC分类号： H03F3/45183 , H01L27/0629 , H01L27/0811 , H01L27/088 , H03F2203/45352 , H03F2203/45371 , H03F2203/45486 , H03M1/0682 , H03M1/0695 , H03M1/442
摘要：　差動電圧配線(W101a)は、差動トランジスタ(T101a,T101a,…)のうち使用するトランジスタのゲート電極を入力電圧(Vinn)を受ける入力ノードに電気的に接続し、差動電圧配線(W101b)は、差動トランジスタ(T101b,T101b,…)のうち使用するトランジスタのゲート電極を入力電圧(Vinp)を受ける入力ノードに電気的に接続する。バイアス電圧配線(W102)は、電流源トランジスタ(T102,T102,…)のうち使用するトランジスタのゲート電極をバイアス電圧(VBN)を受けるバイアスノードに電気的に接続し、バイアス電圧配線(W103)は、負荷トランジスタ(T103a,T103a,…,T103b,T103b,…)のうち使用するトランジスタのゲート電極をバイアス電圧(VBP)を受けるバイアスノードに電気的に接続する。
摘要翻译：差分电压布线（W101a）将要用于差分晶体管（T101a，T101a）的晶体管的栅电极与接收输入电压（Vinn）的输入节点电连接，并且差分电压布线（W101b）电连接用于输出节点接收输入电压（Vinp）的差分晶体管（T101b，T101b）使用的晶体管的栅电极。偏置电压布线（W102）将用于电流源晶体管（T102，T102）的晶体管的栅电极与接收偏置电压（VBN）的偏置节点和偏置电压布线（W103）电连接用于偏置节点接收偏置电压（VBP）的用于负载晶体管（T103a，T103a，T103b，T103b）的晶体管的栅电极。

7. 发明申请

WO2008132509A3 BIPOLAR TRANSISTOR DRIVERS 审中-公开
标题翻译：双极晶体管驱动器
公开(公告)号：WO2008132509A3
公开(公告)日：2008-12-24
申请号：PCT/GB2008050300
申请日：2008-04-25
申请人： CAMBRIDGE SEMICONDUCTOR LTD , GARNER DAVID M , LALITHAMBIKA VINOD A , RYAN PAUL , JACQUES RUSSELL
发明人： GARNER DAVID M , LALITHAMBIKA VINOD A , RYAN PAUL , JACQUES RUSSELL
IPC分类号： H03K17/082
CPC分类号： H03K17/0422 , H02M3/33507 , H03F3/2171 , H03F3/45183 , H03F2203/45322 , H03F2203/45352 , H03F2203/45396 , H03F2203/45466 , H03F2203/45506 , H03K17/0406 , H03K17/0826 , H03K17/0828 , H03K17/567 , H03K17/64 , Y02B70/1433
摘要： We describe a switching power converter comprising a bipolar switching device (BJT or IGBT) switching an inductive load, and including a closed-loop control system. The control system comprises a voltage sensing system to sense a voltage on a collector terminal of the sw itching device and provide a voltage sense signal; a controller; and a drive modulation system coupled to an output of the controller for modulating a drive to the control terminal of said bipolar switching device responsive to a controller control signal; wherein said controller is configured to monitor changes in the sensed voltage during a period when said switching device is switched on and to control said drive modulation system to control the degree of saturation of said bipolar switching device when the device is switched on and hence improve turn-off times.
摘要翻译：我们描述了包括切换感性负载的双极开关器件（BJT或IGBT）以及包括闭环控制系统的开关功率转换器。该控制系统包括：电压感测系统，用于感测开关装置的集电极端子上的电压并提供电压感测信号; 控制器; 以及驱动调制系统，其耦合到所述控制器的输出端，用于响应于控制器控制信号来调制到所述双极开关装置的控制端子的驱动; 其中所述控制器被配置成监测所述开关装置接通期间的感测电压的变化，并且控制所述驱动调制系统以在所述装置接通时控制所述双极开关装置的饱和度并因此改善转向 - 时间。

8. 发明申请

WO2008124347A1 DIFFERENTIAL AMPLIFIER WITH ACTIVE POST-DISTORTION LINEARIZATION 审中-公开
标题翻译：具有主动后失真线性化的差分放大器
公开(公告)号：WO2008124347A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/058710
申请日：2008-03-28
申请人： QUALCOMM INCORPORATED , KIM, Namsoo , BARNETT, Kenneth Charles , APARIN, Vladimir
发明人： KIM, Namsoo , BARNETT, Kenneth Charles , APARIN, Vladimir
IPC分类号： H03F1/32 , H03F1/22 , H03F1/26 , H03F3/45 , H03G1/00
CPC分类号： H03F1/3211 , H03F1/22 , H03F1/223 , H03F1/26 , H03F1/3205 , H03F1/3276 , H03F3/45188 , H03F2200/294 , H03F2200/372 , H03F2200/456 , H03F2200/489 , H03F2200/492 , H03F2203/45296 , H03F2203/45311 , H03F2203/45352 , H03F2203/45386 , H03F2203/45481 , H04B1/525
摘要： A differential amplifier, (300) which has good linearity and noise performance, includes a first side that includes first(310), second, (320) third(330), and fourth(340) transistors and an inductor (350). The first(310) and second(320) transistors are coupled as a first cascode pair, and the third (330) and fourth (340) transistors are coupled as a second cascode pair. The third transistor (330) has its gate coupled to the source of the second transistor (320), and the fourth transistor (340)has its drain coupled to the drain of the second transistor (320). The first transistor (310) provides signal amplification. The second transistor (320) provides load isolation and generates an intermediate signal for the third transistor (330). The third transistor (330) generates distortion components used to cancel third order distortion component generated by the first transistor (310). The inductor (350) provides source degeneration for the first transistor (310) and improves distortion cancellation. The sizes of the second (320) and third (330) transistors are selected to reduce gain loss and achieve good linearity for the amplifier. The differential amplifier also may include a second side that functions similarly to the first side.
摘要翻译：具有良好线性度和噪声性能的差分放大器（300）包括第一侧，其包括第一（310），第二，（320）第三（330）和第四（340）晶体管和电感器（350）。第一（310）和第二（320）晶体管作为第一共源共栅对耦合，并且第三（330）和第四（340）晶体管作为第二共源共栅对耦合。第三晶体管（330）的栅极耦合到第二晶体管（320）的源极，并且第四晶体管（340）的漏极耦合到第二晶体管（320）的漏极。第一晶体管（310）提供信号放大。第二晶体管（320）提供负载隔离并产生用于第三晶体管（330）的中间信号。第三晶体管（330）产生用于消除由第一晶体管（310）产生的三阶失真分量的失真分量。电感器（350）为第一晶体管（310）提供源极退化并改善失真消除。选择第二（320）和第三（330）晶体管的尺寸以减小增益损耗并且实现放大器的良好线性度。差分放大器还可以包括与第一侧类似地起作用的第二侧。

9. 发明申请

WO2008014417A2 ACTIVELY COMPENSATED BUFFERING FOR HIGH SPEED CURRENT MODE LOGIC DATA PATH 审中-公开
标题翻译：用于高速电流模式逻辑数据路径的补偿缓冲
公开(公告)号：WO2008014417A2
公开(公告)日：2008-01-31
申请号：PCT/US2007/074518
申请日：2007-07-26
申请人： PARADE TECHNOLOGIES, LTD. , QU, Ming , YU, Quan
发明人： QU, Ming , YU, Quan
IPC分类号： H03K19/094
CPC分类号： H03K19/01707 , H03F1/483 , H03F3/45183 , H03F2200/36 , H03F2203/45248 , H03F2203/45318 , H03F2203/45352 , H03F2203/45374 , H03F2203/45638 , H03F2203/45702 , H03K19/018514
摘要： An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.
摘要翻译：积极补偿的CML电路包括CML缓冲电路和带宽扩展电路。 CML缓冲电路包括第一MOS晶体管和差分对配置中的第二MOS晶体管。第一负载电阻器在第一输出端子处耦合到第一MOS晶体管漏极，并且第二负载电阻器在第二输出端子耦合到第二MOS晶体管漏极。带宽扩展电路以源跟随器配置耦合到CML缓冲电路。带宽扩展电路包括第三MOS晶体管和第四MOS晶体管。电容器耦合在第三MOS晶体管源极和第四MOS晶体管源极之间。第四MOS晶体管和第三MOS晶体管在第一输出端和第二输出端产生高通功能。

10. 发明申请

WO2008006069A2 PRE-DISTORTION APPARATUS 审中-公开
标题翻译：预设装置
公开(公告)号：WO2008006069A2
公开(公告)日：2008-01-10
申请号：PCT/US2007072957
申请日：2007-07-06
申请人： SCINTERA NETWORKS INC , KEERTHI ARVIND , GOVINDARAJAN MADABUSI , KUMAR VIJAY P , CHOMA JOHN , SHANBHAG ABHIJIT
发明人： KEERTHI ARVIND , GOVINDARAJAN MADABUSI , KUMAR VIJAY P , CHOMA JOHN , SHANBHAG ABHIJIT
IPC分类号： H04L25/49
CPC分类号： H04L27/368 , H03F1/0222 , H03F1/0266 , H03F1/3211 , H03F1/3247 , H03F1/3258 , H03F3/45183 , H03F2200/102 , H03F2200/369 , H03F2200/451 , H03F2203/45352
摘要： Pre-distortion apparatuses and methods for a non-linear component are provided. The apparatus comprises an adaptive block for generating a plurality of correlation coefficients, which are used to weight a plurality of synthesis work functions to pre-distort a given signal. The adaptive block can be driven by an error signal generated from a feedback signal from the non-linear component output signal and a delayed version of the input signal. The apparatus is capable of being operated directly at radio frequency. Also provided are apparatuses and methods for generation of quadrature signals, transconductance amplification employing negative resistance, variable-gain amplification, and envelope detection.
摘要翻译：提供了用于非线性分量的预失真装置和方法。该装置包括用于产生多个相关系数的自适应块，其用于加权多个合成工作函数以对给定信号进行预失真。自适应块可以由从非线性分量输出信号的反馈信号和输入信号的延迟版本产生的误差信号驱动。该装置能够以射频直接操作。还提供了用于产生正交信号，采用负电阻的跨导放大，可变增益放大和包络检测的装置和方法。

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