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    • 1. 发明申请
    • MULTI-MODE LOW NOISE AMPLIFIER WITH TRANSFORMER SOURCE DEGENERATION
    • 具有变压器源变形的多模低噪声放大器
    • WO2011011754A1
    • 2011-01-27
    • PCT/US2010/043153
    • 2010-07-23
    • QUALCOMM IncorporatedTASIC, AleksandarDENG, JunxiongJIN, Zhang
    • TASIC, AleksandarDENG, JunxiongJIN, Zhang
    • H03F1/32H03F3/193H03F3/68
    • H03F1/3205H03F1/223H03F3/193H03F3/45179H03F3/68H03F2200/492
    • A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.
    • 描述了具有变压器源变性的多模低噪声放大器(LNA)。 在示例性设计中,多模LNA包括第一,第二和第三晶体管以及第一和第二电感器。 第一晶体管的源极耦合到第一电感器,放大输入信号,并以第一模式提供第一放大信号。 第二晶体管的源极耦合到第二电感器,放大输入信号,并以第二模式提供第二放大信号。 第三晶体管的源极耦合到第二电感器。 第一和第三晶体管以第三模式分别接收输入信号并且分别通过第一和第二电感器传导电流。 第一晶体管观察由第一和第二电感器形成的变压器的源极退化,放大输入信号,并在第三模式中提供第三放大信号。
    • 2. 发明申请
    • MULTI-LINEARITY MODE LNA HAVING A DEBOOST CURRENT PATH
    • 具有DEBOOST电流路径的多线性模式LNA
    • WO2009088813A2
    • 2009-07-16
    • PCT/US2008/088382
    • 2008-12-27
    • QUALCOMM IncorporatedCHANG, Li-chung
    • CHANG, Li-chung
    • H03F1/32
    • H03F1/3205H03F1/223H03F1/3252H03F3/72H03F2200/492
    • A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and/or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity.
    • 修正导数叠加(MDS)低噪声放大器(LNA)包括主电流路径和消除电流路径。 取消路径中的三阶失真用于消除主路径中的三阶失真。 在一个新颖的方面,对于两个电流路径中的每一个,存在单独的源极退化电感器,从而有助于调谐一个电流路径而不影响另一个电流路径。 在第二个新颖的方面,提供了不穿过LNA负载的去桥电流路径。 去抖动电流允许增加负反馈而不产生余量问题。 在第三个新颖的方面,消除电流路径和/或去桥电流路径可编程地被禁用以降低功耗并改善不需要高线性度的操作模式中的噪声系数。
    • 4. 发明申请
    • FREQUENCY DIVIDER CIRCUITS
    • 频率分路电路
    • WO2007085867A1
    • 2007-08-02
    • PCT/GB2007/050016
    • 2007-01-15
    • FUTURE WAVES UK LIMITEDMILLER, Robin, James
    • MILLER, Robin, James
    • H03K23/66H03K23/54
    • H03K23/544G06F1/3203G06F1/3287H03F3/189H03F3/45188H03F2200/294H03F2200/372H03F2200/489H03F2200/492Y02D10/126Y02D10/171
    • A circuit for deriving an output clock signal from an input clock signal, the output clock 5 signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality o f latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of 10 the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.
    • 用于从输入时钟信号导出输出时钟信号的电路,输出时钟5信号的频率是输入时钟信号的频率的1 / N,其中N是奇数。 电路包括被配置为锁存环的多个锁存器,锁存器被连续地对配置,每对锁存器包括第一锁存器,其中第一锁存器接通输入时钟信号的上升沿或下降沿之一,以及第二锁存器, 将输入时钟信号的上升沿或下降沿的另一个切换为10。 RS触发器被耦合以在其设置和复位输入中的一个处接收来自在上升沿上接通的锁存环的输出,并且在另一个设置和复位输入处,来自锁存环的输出被接通 一个下降的边缘。 所述输出时钟信号被提供在RS触发器的输出处。
    • 9. 发明申请
    • SPLIT AMPLIFIERS WITH IMPROVED LINEARITY
    • 具有改进线性的分立放大器
    • WO2014150333A1
    • 2014-09-25
    • PCT/US2014/022976
    • 2014-03-11
    • QUALCOMM INCORPORATED
    • YOUSSEF, Ahmed, A.CHANG, Li-Chung
    • H03F1/22H03F1/32H03F1/56H03F3/21H03F3/72H03F3/193H03F3/24H03F3/68
    • H03F3/68H03F1/223H03F1/3205H03F1/56H03F3/193H03F3/211H03F3/245H03F3/72H03F2200/489H03F2200/492H03F2200/541H03G1/0023
    • Split amplifiers with configurable gain and linearization circuitry are disclosed. An apparatus includes first (430) and second (440) amplifier circuits and a linearization circuit (420), which may be part of an amplifier. The first (430) and second (440) amplifier circuits are coupled in parallel and to an amplifier input (X). The linearization circuit (420) is also coupled to the amplifier input (X). The first (430) and second (440) amplifier circuits are enabled in a high-gain mode. One of the first (430) and second (440) amplifier circuits is enabled in a low-gain mode. The linearization circuit (420) is enabled in the second mode and disabled in the first mode. The amplifier is split into multiple sections. Each section includes an amplifier circuit and is a fraction of the amplifier. High linearly may be obtained using one amplifier circuit and the linearization circuit in the low-gain mode.
    • 公开了具有可配置增益和线性化电路的分路放大器。 一种装置包括第一(430)和第二(440)放大器电路和线性化电路(420),其可以是放大器的一部分。 第一(430)和第二(440)放大器电路并联耦合到放大器输入(X)。 线性化电路(420)也耦合到放大器输入(X)。 第一(430)和第二(440)放大器电路在高增益模式下使能。 第一(430)和第二(440)放大器电路之一在低增益模式下使能。 线性化电路(420)在第二模式下使能并且在第一模式中被禁用。 放大器分为多个部分。 每个部分包括放大器电路,并且是放大器的一小部分。 可以使用一个放大器电路和低增益模式下的线性化电路获得高线性。