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1. 发明申请

WO2007016552A1 AMPLIFIER WITH ACTIVE POST-DISTORTION LINEARIZATION 审中-公开
标题翻译：具有主动后失真线性化的放大器
公开(公告)号：WO2007016552A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/029905
申请日：2006-07-31
申请人： QUALCOMM INCORPORATED , KIM, Namsoo , BARNETT, Kenneth, Charles , APARIN, Vladimir
发明人： KIM, Namsoo , BARNETT, Kenneth, Charles , APARIN, Vladimir
IPC分类号： H03F1/32 , H03F1/22
CPC分类号： H03F1/223 , H03F1/3205 , H03F1/3276 , H03F2200/294 , H03F2200/372 , H04B1/525
摘要： An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.
摘要翻译：具有良好线性度和噪声性能的放大器包括第一，第二，第三和第四晶体管和电感器。第一和第二晶体管作为第一共源共栅对耦合，并且第三和第四晶体管作为第二共源共栅对耦合。第三晶体管的栅极耦合到第二晶体管的源极，并且第四晶体管的漏极耦合到第二晶体管的漏极。第一个晶体管提供信号放大。第二晶体管提供负载隔离并为第三晶体管产生中间信号。第三晶体管产生用于消除由第一晶体管产生的三阶失真分量的失真分量。电感器为第一晶体管提供源极退化，并改善失真消除。选择第二和第三晶体管的尺寸以减小增益损耗并且获得放大器的良好线性度。

2. 发明申请

WO2008124347A1 DIFFERENTIAL AMPLIFIER WITH ACTIVE POST-DISTORTION LINEARIZATION 审中-公开
标题翻译：具有主动后失真线性化的差分放大器
公开(公告)号：WO2008124347A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/058710
申请日：2008-03-28
申请人： QUALCOMM INCORPORATED , KIM, Namsoo , BARNETT, Kenneth Charles , APARIN, Vladimir
发明人： KIM, Namsoo , BARNETT, Kenneth Charles , APARIN, Vladimir
IPC分类号： H03F1/32 , H03F1/22 , H03F1/26 , H03F3/45 , H03G1/00
CPC分类号： H03F1/3211 , H03F1/22 , H03F1/223 , H03F1/26 , H03F1/3205 , H03F1/3276 , H03F3/45188 , H03F2200/294 , H03F2200/372 , H03F2200/456 , H03F2200/489 , H03F2200/492 , H03F2203/45296 , H03F2203/45311 , H03F2203/45352 , H03F2203/45386 , H03F2203/45481 , H04B1/525
摘要： A differential amplifier, (300) which has good linearity and noise performance, includes a first side that includes first(310), second, (320) third(330), and fourth(340) transistors and an inductor (350). The first(310) and second(320) transistors are coupled as a first cascode pair, and the third (330) and fourth (340) transistors are coupled as a second cascode pair. The third transistor (330) has its gate coupled to the source of the second transistor (320), and the fourth transistor (340)has its drain coupled to the drain of the second transistor (320). The first transistor (310) provides signal amplification. The second transistor (320) provides load isolation and generates an intermediate signal for the third transistor (330). The third transistor (330) generates distortion components used to cancel third order distortion component generated by the first transistor (310). The inductor (350) provides source degeneration for the first transistor (310) and improves distortion cancellation. The sizes of the second (320) and third (330) transistors are selected to reduce gain loss and achieve good linearity for the amplifier. The differential amplifier also may include a second side that functions similarly to the first side.
摘要翻译：具有良好线性度和噪声性能的差分放大器（300）包括第一侧，其包括第一（310），第二，（320）第三（330）和第四（340）晶体管和电感器（350）。第一（310）和第二（320）晶体管作为第一共源共栅对耦合，并且第三（330）和第四（340）晶体管作为第二共源共栅对耦合。第三晶体管（330）的栅极耦合到第二晶体管（320）的源极，并且第四晶体管（340）的漏极耦合到第二晶体管（320）的漏极。第一晶体管（310）提供信号放大。第二晶体管（320）提供负载隔离并产生用于第三晶体管（330）的中间信号。第三晶体管（330）产生用于消除由第一晶体管（310）产生的三阶失真分量的失真分量。电感器（350）为第一晶体管（310）提供源极退化并改善失真消除。选择第二（320）和第三（330）晶体管的尺寸以减小增益损耗并且实现放大器的良好线性度。差分放大器还可以包括与第一侧类似地起作用的第二侧。

3. 发明申请

WO2010111542A1 SPUR ATTENUATION DEVICES, SYSTEMS, AND METHODS 审中-公开
标题翻译： SPUR衰减设备，系统和方法
公开(公告)号：WO2010111542A1
公开(公告)日：2010-09-30
申请号：PCT/US2010/028738
申请日：2010-03-25
申请人： QUALCOMM INCORPORATED , APARIN, Vladimir , KIM, Namsoo , MATHE, Lennart, K.
发明人： APARIN, Vladimir , KIM, Namsoo , MATHE, Lennart, K.
IPC分类号： H04B1/10 , H04B1/12 , H04B1/52 , H04B1/04
CPC分类号： H04B1/525 , H03F1/34 , H03F3/24 , H04B1/0475 , H04B1/109 , H04B1/123 , H04B2001/0433
摘要： Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal.
摘要翻译：本发明的示例性实施例公开了信号滤波。在示例性实施例中，滤波器装置可以包括可操作地耦合在输入端和输出端之间并被配置为接收包括期望分量和至少一个不需要的频率分量的输入信号的减法器。滤波器装置还可以包括反馈回路，其被配置为从减法器接收输入信号和输出信号中的至少一个，并将包括至少一个不期望的分量的反馈信号传送到减法器。反馈信号的每个不期望的分量对应于输入信号的相关不期望的分量。此外，减法器从输入信号中减去反馈信号并传送输出信号。

4. 发明申请

WO2012006470A1 COMMUNICATION AND SYNAPSE TRAINING METHOD AND HARDWARE FOR BIOLOGICALLY INSPIRED NETWORKS 审中-公开
标题翻译：通信和仿真培训方法和生物信息网络的硬件
公开(公告)号：WO2012006470A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/043257
申请日：2011-07-07
申请人： QUALCOMM Incorporated , APARIN, Vladimir , TANG, Yi
发明人： APARIN, Vladimir , TANG, Yi
IPC分类号： G06N3/063
CPC分类号： G06N3/0635 , G06N3/02 , G06N3/06 , G06N3/08 , G06N99/005
摘要： Certain embodiments of the present disclosure support techniques for training of synapses in biologically inspired networks. Only one device based on a memristor can be used as a synaptic connection between a pair of neurons. The training of synaptic weights can be achieved with a low current consumption. A proposed synapse training circuit may be shared by a plurality of incoming/outgoing connections, while only one digitally implemented pulse-width modulation (PWM) generator can be utilized per neuron circuit for generating synapse-training pulses. Only up to three phases of a slow clock can be used for both the neuron-to-neuron communications and synapse training. Some special control signals can be also generated for setting up synapse training events. By means of these signals, the synapse training circuit can be in a high-impedance state outside the training events, thus the synaptic resistance (i.e., the synaptic weight) is not affected outside the training process.
摘要翻译：本公开的某些实施例支持在生物启发网络中训练突触的技术。只有一个基于忆阻器的设备可以用作一对神经元之间的突触连接。突触体重的训练可以用低电流消耗来实现。所提出的突触训练电路可以由多个输入/输出连接共享，而每个神经元电路只能使用一个数字实现的脉宽调制（PWM）发生器来产生突触训练脉冲。只有三个阶段的慢时钟可用于神经元到神经元通信和突触训练。还可以生成一些特殊控制信号来设置突触训练事件。通过这些信号，突触训练电路可以处于训练事件之外的高阻抗状态，因此突触电阻（即突触重量）在训练过程之外不受影响。

5. 发明申请

WO2012006465A1 METHODS AND SYSTEMS FOR CMOS IMPLEMENTATION OF NEURON SYNAPSE 审中-公开
标题翻译：神经元SYNPSPS的CMOS实现方法与系统
公开(公告)号：WO2012006465A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/043251
申请日：2011-07-07
申请人： QUALCOMM Incorporated , APARIN, Vladimir , LEVIN, Jeffrey, A.
发明人： APARIN, Vladimir , LEVIN, Jeffrey, A.
IPC分类号： G06N3/063
CPC分类号： G06N3/0635 , G06N3/049 , G11C11/54
摘要： Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.
摘要翻译：本发明的某些实施例支持用正和/或负的突触权重进行神经元突触功率有效实现的技术。

6. 发明申请

WO2010151894A1 FEEDBACK SYSTEM WITH IMPROVED STABILITY 审中-公开
标题翻译：反馈系统具有改进的稳定性
公开(公告)号：WO2010151894A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040252
申请日：2010-06-28
申请人： QUALCOMM Incorporated , APARIN, Vladimir , BALLANTYNE, Gary, John
发明人： APARIN, Vladimir , BALLANTYNE, Gary, John
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift.
摘要翻译：描述了提高反馈系统稳定性的技术。在示例性设计中，反馈系统包括前向路径和反馈路径。正向路径接收输入信号和旋转的反馈信号，并提供具有相移的输出信号。反馈路径接收输出信号，产生反馈信号，并且使反馈信号旋转以获得具有至少部分移相消除的旋转的反馈信号。在另一示例性设计中，反馈系统包括前向路径和反馈回路。前向路径接收组合信号并提供具有相移的输出信号。反馈回路基于输入信号和输出信号产生误差信号，基于误差信号和输入信号产生组合信号，并执行相位旋转以去除至少部分相移。

7. 发明申请

WO2010151569A1 TRANSMITTER ARCHITECTURES 审中-公开
标题翻译：发射机架构
公开(公告)号：WO2010151569A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/039612
申请日：2010-06-23
申请人： QUALCOMM INCORPORATED , APARIN, Vladimir
发明人： APARIN, Vladimir
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： Techniques for generating a transmit (TX) signal with improved characteristics in the presence of interference such as noise and distortion. In one aspect, the TX output signal is used to generate a reconstructed signal having the characteristics of the interference, and the reconstructed signal is subtracted from the baseband TX signal. The reconstructed signal may be generated by high-pass filtering the TX output signal at baseband. Alternatively, the reconstructed signal may be generated from a reference signal Ref derived from the baseband TX signal.
摘要翻译：用于在存在诸如噪声和失真的干扰的情况下产生具有改进特性的发射（TX）信号的技术。一方面，TX输出信号用于产生具有干扰特性的重构信号，并且从基带TX信号中减去重构信号。重构的信号可以通过在基带处对TX输出信号进行高通滤波来产生。或者，可以从从基带TX信号导出的参考信号Ref生成重构信号。

8. 发明申请

WO2009111346A1 DYNAMIC REFERENCE FREQUENCY FOR FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译：分段N相锁定环路的动态参考频率
公开(公告)号：WO2009111346A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/035577
申请日：2009-02-27
申请人： QUALCOMM Incorporated , CICCARELLI, Steven C. , BOSSU, Frederic , APARIN, Vladimir , WANG, Kevin H.
发明人： CICCARELLI, Steven C. , BOSSU, Frederic , APARIN, Vladimir , WANG, Kevin H.
IPC分类号： H03L7/197 , H04B15/06
CPC分类号： H03L7/1974
摘要： Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
摘要翻译：在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合以不良的方式。在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。

9. 发明申请

WO2012177913A1 METHOD AND APPARATUS FOR A LOCAL COMPETITIVE LEARNING RULE THAT LEADS TO SPARSE CONNECTIVITY 审中-公开
标题翻译：针对当地竞争性学习的方法和设备引导疏漏的连接性
公开(公告)号：WO2012177913A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/043594
申请日：2012-06-21
申请人： QUALCOMM INCORPORATED , APARIN, Vladimir
发明人： APARIN, Vladimir
IPC分类号： G06N3/08
CPC分类号： G06N3/08 , G05B13/024 , G05B13/027 , G06N3/06 , G06N3/088
摘要： Certain aspects of the present disclosure support a local competitive learning rule applied in a computational network that leads to sparse connectivity among processing units of the network. The present disclosure provides a modification to the Oja learning rule, modifying the constraint on the sum of squared weights in the Oja rule. This constraining can be intrinsic and local as opposed to the commonly used multiplicative and subtractive normalizations, which are explicit and require the knowledge of all input weights of a processing unit to update each one of them individually. The presented rule provides convergence to a weight vector that is sparser (i.e., has more zero elements) than the weight vector learned by the original Oja rule. Such sparse connectivity can lead to a higher selectivity of processing units to specific features, and it may require less memory to store the network configuration and less energy to operate it.
摘要翻译：本公开的某些方面支持在计算网络中应用的本地竞争性学习规则，其导致网络的处理单元之间的稀疏连接。本公开提供了对Oja学习规则的修改，修改了Oja规则中的平方权重之和的约束。这种约束可以是内在的和局部的，而不是通常使用的乘法和减法规范化，它们是显式的，并且需要知道处理单元的所有输入权重以分别更新它们中的每一个。所呈现的规则提供了与由原始Oja规则学习的权重向量相比更加稀疏（即，具有更多零个元素）的权重向量的收敛。这种稀疏连接可以导致处理单元对特定特征的更高选择性，并且可能需要更少的存储器来存储网络配置和较少的能量来操作它。

10. 发明申请

WO2012162663A1 METHOD AND APPARATUS FOR UNSUPERVISED TRAINING OF INPUT SYNAPSES OF PRIMARY VISUAL CORTEX SIMPLE CELLS AND OTHER NEURAL CIRCUITS 审中-公开
标题翻译：主要视觉CORTEX简单细胞和其他神经电路输入信号的不间断训练的方法和装置
公开(公告)号：WO2012162663A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/039704
申请日：2012-05-25
申请人： QUALCOMM Incorporated , APARIN, Vladimir
发明人： APARIN, Vladimir
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： Certain aspects of the present disclosure present a technique for unsupervised training of input synapses of primary visual cortex (V1) simple cells and other neural circuits. The proposed unsupervised training method utilizes simple neuron models for both Retinal Ganglion Cell (RGC) and V1 layers. The model simply adds the weighted inputs of each cell, wherein the inputs can have positive or negative values. The resulting weighted sums of inputs represent activations that can also be positive or negative. In an aspect of the present disclosure, the weights of each V1 cell can be adjusted depending on a sign of corresponding RGC output and a sign of activation of that V1 cell in the direction of increasing the absolute value of the activation. The RGC-to-V1 weights can be positive and negative for modeling ON and OFF RGCs, respectively.
摘要翻译：本公开的某些方面提供了用于无监督训练初级视皮层（V1）简单细胞和其他神经电路的输入突触的技术。提出的无监督训练方法使用简单的神经元模型用于视网膜神经节细胞（RGC）和V1层。该模型简单地添加每个单元的加权输入，其中输入可以具有正值或负值。所得的加权输入总和代表也可以是正或负的激活。在本公开的一方面，可以根据对应的RGC输出的符号和在增加激活的绝对值的方向激活该V1小区的符号来调整每个V1小区的权重。 RGC-to-V1权重可以分别为ON和OFF RGC的正负值。

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