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1. 发明申请

WO01061759A1 SEMICONDUCTOR DEVICE FOR LOW VOLTAGE PROTECTION WITH LOW CAPACITANCE 审中-公开
标题翻译：低电容低电压保护的半导体器件
公开(公告)号：WO01061759A1
公开(公告)日：2001-08-23
申请号：PCT/US2001/004906
申请日：2001-02-15
IPC分类号： H01L27/02 , H01L29/74 , H01L29/747 , H01L29/87 , H01L31/111
CPC分类号： H01L29/7424 , H01L27/0259 , H01L27/0262 , H01L29/747 , H01L29/87
摘要： A semiconductor thyristor device (110) that incorporates buried regions (112) spaced around an emitter region (114). By spacing the buried regions (112) around the emitter region (114), current carriers emitted from the buried regions are distributed over a large area of the emitter region (114), thereby providing a high current capability during initial turn on of the device. In order to achieve low breakover voltage devices, the buried regions (112) are offset laterally with respect to the respective emitter regions (114). The low voltage thyristor device exhibits a low capacitance for operating with high speed, low voltage signals. The device capacitance is reduced by utilizing a plurality of buried regions (112), each formed having a relatively small area junction with the base region (118).
摘要翻译：一种半导体晶闸管器件（110），其包括围绕发射极区域（114）间隔开的掩埋区域（112）。通过围绕发射极区域（114）间隔埋置区域（112），从掩埋区域发射的电流载流子分布在发射极区域（114）的大面积上，从而在器件的初始接通期间提供高电流能力。为了实现低突破电压器件，埋入区域（112）相对于相应的发射极区域（114）横向偏移。低电压晶闸管器件具有低电容，用于高速，低电压信号的工作。通过利用多个掩埋区域（112）来减小器件电容，每个掩埋区域形成为具有与基极区域（118）相对较小的面积结。

2. 发明申请

WO2015154908A1 TURN-OFF POWER SEMICONDUCTOR DEVICE WITH IMPROVED CENTERING AND FIXING OF A GATE RING, AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有改进的门环的中心和固定的关闭功率半导体器件及其制造方法
公开(公告)号：WO2015154908A1
公开(公告)日：2015-10-15
申请号：PCT/EP2015/053697
申请日：2015-02-23
申请人： ABB TECHNOLOGY AG
发明人： RAVENER, Hendrik , WIKSTROEM, Tobias , AMSTUTZ, Hermann , MEIER, Norbert
IPC分类号： H01L23/051 , H01L23/31
CPC分类号： H01L29/745 , H01L21/565 , H01L23/051 , H01L23/3185 , H01L29/45 , H01L29/66363 , H01L29/7416 , H01L29/7424 , H01L29/744 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a turn-off power semiconductor device (1) having a wafer (10) with an active region and a termination region surrounding the active region, a rubber ring (70) as an edge passivation for the wafer (10) and a gate ring (60) placed on a ring-shaped gate contact (40) on the termination region for contacting the gate electrodes of at least one thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device (1) of the invention, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring (70). In the invention the area consumed by the ring-shaped gate contact (40) on the termination or edge region can be minimized. The upper surface of the gate ring (60) and the upper surface of the rubber ring (70) form a continuous surface extending in a plane parallel to the first main side (11) of the wafer (10). In a method for manufacturing the device, the gate ring (60) is used as an inner sidewall of a mold for molding the rubber ring (70).
摘要翻译：本发明涉及一种具有晶圆（10）的截止功率半导体器件（1），其具有有源区和围绕有源区的端接区，作为用于晶片（10）的边缘钝化的橡胶环（70）以及放置在终端区上的环形栅极接触件（40）上的栅极环（60），用于接触形成在晶片有源区域中的至少一个晶闸管电池的栅电极。在本发明的关断功率半导体装置（1）中，门环的外周面与橡胶环接触，以限定橡胶环（70）的内边界。在本发明中，环形门接触件（40）在终端或边缘区域上消耗的面积可以最小化。闸环（60）的上表面和橡胶环（70）的上表面形成在与晶片（10）的第一主侧（11）平行的平面中延伸的连续表面。在制造该装置的方法中，门环（60）用作模制橡胶环（70）的模具的内侧壁。

3. 发明申请

WO1998015010A1 THYRISTOR WITH BREAKDOWN REGION 审中-公开
标题翻译：具有突破性区晶闸管
公开(公告)号：WO1998015010A1
公开(公告)日：1998-04-09
申请号：PCT/DE1997002237
申请日：1997-09-29
申请人： EUPEC EUROPÄISCHE GESELLSCHAFT FÜR LEISTUNGSHALBLEITER MBH + CO. KG , RUFF, Martin , SCHULZE, Hans-Joachim
发明人： EUPEC EUROPÄISCHE GESELLSCHAFT FÜR LEISTUNGSHALBLEITER MBH + CO. KG
IPC分类号： H01L29/74
CPC分类号： H01L21/263 , H01L29/1016 , H01L29/102 , H01L29/32 , H01L29/7424
摘要： The invention relates to a thyristor formed by a semiconductor body (1) with a base zone (2) on the anode side of the first mode of conductivity and at least one base zone (3) on the cathode side of the opposite second mode of conductivity, with emitter zones (7, 8) on both the anode and the cathode sides, with at least one region (6) in the base zone on the cathode side (3), which, owing to its geometry, has a reduced breakdown voltage as compared to the other regions of the base zone on the cathode side (3) and the border of the semiconductor body (1). The thyristor presents on the anode side beneath the region with reduced channeling current (6) at least one recombination zone (9) with decreased service life of the free charge carrier.
摘要翻译：本发明涉及包括半导体本体中的半导体闸流管（1），其具有阳极基座区（2）的第一导电类型和至少一个阴极基区（3）的相反的第二导电型，其具有阳极和阴极发射极区（7，8），与至少一个区域（6）在具有相对于阴极侧基区（3）和半导体本体（1）通过其几何形状的边缘的其他区域中的阴极基区（3）的击穿电压降低。阳极侧，在至少一个复合区域（9），击穿电压降低（6）的区域下方的晶闸管与自由载流子的寿命缩短。

4. 发明申请

WO2012093146A2 METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT COMPRISING AN INTEGRATED LATERAL RESISTOR 审中-公开
标题翻译：法用于制造半导体COMPONENT具有集成横向电阻
公开(公告)号：WO2012093146A2
公开(公告)日：2012-07-12
申请号：PCT/EP2012050112
申请日：2012-01-04
申请人： INFINEON TECHNOLOGIES BIPOLAR GMBH & CO KG , SCHULZE HANS-JOACHIM , KELLNER-WERDEHAUSEN UWE , BAUER KURT
发明人： SCHULZE HANS-JOACHIM , KELLNER-WERDEHAUSEN UWE , BAUER KURT
CPC分类号： H01L29/102 , H01L29/0646 , H01L29/167 , H01L29/66371 , H01L29/7408 , H01L29/7424 , H01L29/7428 , H01L31/1113
摘要： A description is given of a method for producing a semiconductor component comprising at least one integrated lateral resistor (11), comprising the following steps: providing a semiconductor body (1) composed of a doped semiconductor material of a first conduction type (n) having a doped base zone (4) of a second conduction type (p), which is complementary to the first conduction type, said base zone adjoining a surface of the semiconductor body (1), masking the surface of the semiconductor body (1), wherein at least one cutout (18) having a predefined width is introduced into the mask (16), such that a resistance region (10) of the base zone (4) is at least partly exposed, covering the exposed resistance region (10) with a dopant of the first conduction type (n) in such a way that a thin covering layer (20) of the first conduction type (n) having a high doping concentration is formed on the surface side on the exposed resistance region (10) and driving the applied dopant of the first conduction type (n) into the resistance region (10) in such a way that a thicker layer (21, 22) having a lower doping concentration is formed from the thin covering layer (20) having a high doping concentration.
摘要翻译：制造具有至少一个集成的横向电阻通过以下步骤中描述的半导体器件（11）的方法，包括：第一导电类型（n）的掺杂的半导体材料的提供半导体主体（1）与（1）相邻的该半导体主体的表面上，第二的掺杂的基极区（4），与第一导电型导电类型（p）互补，掩蔽所述半导体主体（1）的表面上，其特征在于，至少一个凹部（18）具有预定宽度被引入到掩模（16），从而使电阻区域至少部分地（4），其与所述第一导电类型的掺杂剂覆盖暴露的电阻区域（10），基极区的暴露（10）（N），使得表面侧的第一导电类型的暴露的电阻区域（10）（薄的沉积层（20） n）与高掺杂浓度形成，并且驱动在b 第一导电型（n）中的阻性区域（10）这样的掺杂剂elegten从具有高杂质浓度的薄沉积层（20），一个较厚的层（21，22）具有较低的掺杂浓度来形成。

5. 发明申请

WO98034282A1 ASYMMETRICAL THYRISTOR 审中-公开
标题翻译：不对称晶闸管
公开(公告)号：WO98034282A1
公开(公告)日：1998-08-06
申请号：PCT/DE1998/000248
申请日：1998-01-28
IPC分类号： H01L29/74 , H01L31/111 , H01L29/36
CPC分类号： H01L29/7428 , H01L29/7424 , H01L29/7432 , H01L31/1113
摘要： Both the cut-off voltage and breakover voltage of conventional thyristors are highly temperature-dependent. The corresponding voltage values can vary by as much as 15 % within the temperature range (5 DEG C - 120 DEG C) in which said thyristors function. In the thyristor described in the invention, ignition is forced about by the punch-through effect, which is independent of temperature (expansion of the space charge region assigned to the p base-/n-base transition (10) to the neighbouring n-base-/p-emitter transition (11)). To ensure that the ignition triggered by punch-through starts at the centre of the thyristor, in n+-stop region (7') the concentration of doping material is considerably reduced in the region (18) situated below the gate electrode (14) in relation to the laterally adjacent area of said stop region (7') extending as far as the edge of the wafer. The effect of this comparably low doping in the central area (18) of the stop region (7') is that in said region the space charge region assigned to the pn transition (10) expands as far as the p+-emitter (8) when a high breakover voltage is applied. As a result, the off-state current rises strongly and the central thyristor area reaches the on state.
摘要翻译：两个反向电压和常规晶闸管的转折电压表现出明显的热行为，相关的温度范围内（5℃ - 120℃）内的相应的电压值可以高达15％而变化。在所提出的晶闸管，开销点火是独立的“穿通”的温度的效果被迫（（相关联的p基极/正 - 基极结10）空间电荷区的程度一直到相邻的n基极/ p-发射极结（11））。到sicherzsutellen通过诱导点火开始在晶闸管的中心“穿通”，在N + -Stoppzone（7“）在的杂质浓度下相对于栅电极的一半（14）位于区域（18）到后来的人的相邻并向上延伸到晶片边缘区域显著降低了停止区（7“）。在停止区（7“）的中央区域（18）的相对较弱的掺杂导致有施加高击穿电压到P +发射极（8），反向电流相应ansgeigt强膨胀过程中与pn结（10）空间电荷区相关联并且在导通状态下的中央晶闸管。

6. 发明申请

WO1997044827A1 THYRISTOR WITH INTEGRATED DU/DT PROTECTION 审中-公开
标题翻译：具有集成DU / dt保护晶闸管
公开(公告)号：WO1997044827A1
公开(公告)日：1997-11-27
申请号：PCT/DE1997000927
申请日：1997-05-07
申请人： SIEMENS AKTIENGESELLSCHAFT , RUFF, Martin , SCHULZE, Hans-Joachim , PFIRSCH, Frank
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L29/74
CPC分类号： H01L29/7424 , H01L29/102 , H01L29/7428
摘要： Too great a dU/dt load on a tyristor can trigger uncontrolled firing in the area of the cathode surface. Because the plasma cannot easily spread out in that area and, consequently, the currency density quickly reaches critical values, the danger exists that local overheating may destroy the tyristor. The thyristor proposed has a centrally located BOD structure and several auxilliary thyristors which surround the BOD structure in a ring form (AG 1-5 (AG = amplifying gate)). Below/Underneath the emmitter area (11) assigned to the innermost auxilliary thyristor (1. AG), the resistance of the base facing the cathode (8) is locally increased. Since the length (L) and the coating resistance of this ring zone (15) decisively influences the dU/dt load capacity of the first auxilliary thyristor (1. AG), these parameters can be suitably dimensioned to ensure that the central thyristor area has the lowest dU/dt sensitivity of the system and, consequently, consistently fires first, when a critical rate of rise in the value of the off-state voltage is reached. This invention can be applied to light-triggered power thyristors.
摘要翻译：在过大的dv / dt应力可以点燃晶闸管这种不受控制的在阴极表面的面积。由于等离子体存在传播不良和电流密度，因此很快达到临界水平，有晶闸管的破坏的局部过热的风险。所提出的晶闸管具有一个位于中心的BOD结构（BOD =盈亏过二极管）和包围环状辅助晶闸管多个BOD结构的（1-5。AG）（AG =放大栅）上。最里面的辅助晶闸管（1 AG）发射极区域（11）相关联的下面局部增大阴极侧基的电阻（8）。由于宽度（L）和所述环形区（15）的薄层电阻决定性地影响所述DU / DT-携带第一辅助晶闸管（1 AG），可以是由这些参数的适当尺寸确保，的容量，中央晶闸管最小的dU / dt的具有该系统的压痛，因此它总是在第一超过所述电压梯度的临界值点燃。光触发晶闸管电源。

7. 发明申请

WO2015183544A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO2015183544A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/030351
申请日：2015-05-12
申请人： OPEL SOLAR, INC. , UNIVERSITY OF CONNECTICUT TECHNOLOGY PARTNERSHIPS & LICENSING
发明人： TAYLOR, Geoff, W.
IPC分类号： H01L29/745 , H01L29/749 , H01L29/15 , G02B6/293
CPC分类号： H01L31/1136 , G02B6/00 , G02B6/12 , G02B6/29338 , G02B6/3596 , G02B6/4295 , G02B6/43 , G02B2006/12145 , H01L27/1443 , H01L29/0834 , H01L29/0839 , H01L29/122 , H01L29/7392 , H01L29/74 , H01L29/7424 , H01L29/745 , H01L29/749 , H01L31/022408 , H01L31/02327 , H01L31/03044 , H01L31/03046 , H01L31/035209
摘要： A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.
摘要翻译：适用于功率应用的半导体器件包括限定从阴极区垂直偏移的阳极区的晶闸管外延层结构，其间具有多个中间区。阳极电极电耦合到阳极区域。阴极电连接到阴极区。在阳极区域和阴极区域之间垂直延伸的可切换电流路径具有导通状态和非导通状态。外延电阻区域电耦合到多个中间区域中的一个并且从其横向延伸。提供具有电耦合到外延电阻区的沟道的FET。 FET可以被配置为通过外延电阻区域将（或从）一个中间区域注入（或去除）电载体，以便在其导通状态和其导通状态之间切换可切换电流路径。

8. 发明申请

WO2014071294A1 ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION 审中-公开
标题翻译：具有隔离SCR的ESD保护电路用于负压运行
公开(公告)号：WO2014071294A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/068276
申请日：2013-11-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SALMAN, Akram, A. , FARBIZ, Farzan , CHATTERJEE, Amitava , WU, Xiaoju
IPC分类号： H01L29/66 , H02H9/00
CPC分类号： H01L27/0262 , H01L29/1012 , H01L29/7424 , H01L29/7436
摘要： A semiconductor controlled rectifier for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.
摘要翻译：公开了一种用于集成电路的半导体可控整流器。半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

9. 发明申请

WO1997016853A1 INSULATED GATE SEMICONDUCTOR DEVICES WITH IMPLANTS FOR IMPROVED RUGGEDNESS 审中-公开
标题翻译：绝缘栅极半导体器件，具有改进的粗糙度的植入物
公开(公告)号：WO1997016853A1
公开(公告)日：1997-05-09
申请号：PCT/US1995014294
申请日：1995-11-02
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , BULUCEA, Constantin , BLANCHAR, Richard, A.
IPC分类号： H01L29/10
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/1095 , H01L29/7424 , H01L29/7808 , H01L29/7811
摘要： Vertical planar and non-planar insulated gate semiconductor device cells having improved ruggedness under drain avalanche conditions are disclosed. The cells employ high concentration implants which are strategically located in the central cell regions. The implants are effective to concentrate the electric field intensity and avalanche current flow in the central cell region and to prevent current flow into the base of a parasitic bipolar transistor, thereby preventing activation of the transistor. Both surface-peaked and subsurface-peaked implants are disclosed.
摘要翻译：公开了在排水雪崩条件下具有改善的耐久性的垂直平面和非平面绝缘栅半导体器件单元。细胞使用高浓度植入物，其在策略上位于中心细胞区域中。植入物有效地将电场强度和雪崩电流集中在中心细胞区域中，并且防止电流流入寄生双极晶体管的基极，从而防止晶体管的激活。公开了表面峰值和地下峰值植入物。

10. 发明申请

WO2016101134A1 一种双向MOS型器件及其制造方法审中-公开
公开(公告)号：WO2016101134A1
公开(公告)日：2016-06-30
申请号：PCT/CN2014/094626
申请日：2014-12-23
申请人：电子科技大学 , 东莞电子科技大学电子信息工程研究院
发明人：张金平 , 李泽宏 , 刘竞秀 , 任敏 , 张波 , 李肇基
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7424 , H01L21/02233 , H01L21/26586 , H01L21/3065 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/408 , H01L29/66325 , H01L29/66386 , H01L29/7394 , H01L29/747 , H01L29/78
摘要：一种双向金属氧化物半导体（MOS）型器件及其制造方法，属于功率半导体器件技术领域。该器件在有源区上层两端具有对称的平面栅MOS结构，在对称的平面栅MOS结构之间具有U型复合漂移区，该U型复合漂移区沿元胞中心左右对称。通过形成的具有对称特性的U型复合漂移区，在一定的元胞宽度下可获得高的器件击穿电压和低的导通压降/电阻特性，是一种双向对称的电场截止型器件；在IGBT工作模式时，是一种具有载流子存储层和场截止层的IGBT器件，在MOS工作模式时，是一种具有减小漂移区电阻高掺杂层和场截止层的MOS器件；通过该U型复合漂移区的复合作用，该结构不会发生器件的横向和纵向穿通击穿，具有高的单位漂移区长度耐压，并具有低的导通压降/电阻特性。

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