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1. 发明申请

WO2015056040A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE STRUCTURES AND METHODS OF MANUFACTURE 审中-公开
标题翻译：静电放电保护装置结构及其制造方法
公开(公告)号：WO2015056040A1
公开(公告)日：2015-04-23
申请号：PCT/IB2013/002714
申请日：2013-10-18
申请人： FREESCALE SEMICONDUCTOR, INC. , LAINE, Jean Philippe , BESSE, Patrice
发明人： LAINE, Jean Philippe , BESSE, Patrice
IPC分类号： H01L29/87 , H01L29/06 , H01L23/29 , H01L29/66 , H01L21/322 , H01L29/74
CPC分类号： H01L27/0262 , H01L21/76 , H01L23/291 , H01L27/0255 , H01L27/0292 , H01L27/1203 , H01L29/0626 , H01L29/0649 , H01L29/66371 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device comprising an SCR -type circuit (300) including a PNP transistor (101) and NPN transistor (106) incorporates a Zener diode (108) which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area (308) of an N-type well (307). One or more diodes (105) connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers (314a, 314b) between doped regions (310, 313, 315) instead of gate oxide technology significantly reduces unwanted leakage currents.
摘要翻译：包括包括PNP晶体管（101）和NPN晶体管（106）的SCR型电路（300）的ESD保护器件包括齐纳二极管（108），其允许电路在相对低的触发电压阈值下操作。齐纳二极管击穿电压由N型阱（307）的掺杂区域（308）中的掺杂水平控制。串联连接在SCR电路和器件的输入/输出端之间的一个或多个二极管（105）有利地提高了SCR电路的快速恢复电压。掺杂区域（310,313,315）之间的氮化物间隔物（314a，314b）代替栅极氧化物技术的使用显着地减少了不必要的漏电流。

2. 发明申请

WO2012093146A2 METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT COMPRISING AN INTEGRATED LATERAL RESISTOR 审中-公开
标题翻译：法用于制造半导体COMPONENT具有集成横向电阻
公开(公告)号：WO2012093146A2
公开(公告)日：2012-07-12
申请号：PCT/EP2012050112
申请日：2012-01-04
申请人： INFINEON TECHNOLOGIES BIPOLAR GMBH & CO KG , SCHULZE HANS-JOACHIM , KELLNER-WERDEHAUSEN UWE , BAUER KURT
发明人： SCHULZE HANS-JOACHIM , KELLNER-WERDEHAUSEN UWE , BAUER KURT
CPC分类号： H01L29/102 , H01L29/0646 , H01L29/167 , H01L29/66371 , H01L29/7408 , H01L29/7424 , H01L29/7428 , H01L31/1113
摘要： A description is given of a method for producing a semiconductor component comprising at least one integrated lateral resistor (11), comprising the following steps: providing a semiconductor body (1) composed of a doped semiconductor material of a first conduction type (n) having a doped base zone (4) of a second conduction type (p), which is complementary to the first conduction type, said base zone adjoining a surface of the semiconductor body (1), masking the surface of the semiconductor body (1), wherein at least one cutout (18) having a predefined width is introduced into the mask (16), such that a resistance region (10) of the base zone (4) is at least partly exposed, covering the exposed resistance region (10) with a dopant of the first conduction type (n) in such a way that a thin covering layer (20) of the first conduction type (n) having a high doping concentration is formed on the surface side on the exposed resistance region (10) and driving the applied dopant of the first conduction type (n) into the resistance region (10) in such a way that a thicker layer (21, 22) having a lower doping concentration is formed from the thin covering layer (20) having a high doping concentration.
摘要翻译：制造具有至少一个集成的横向电阻通过以下步骤中描述的半导体器件（11）的方法，包括：第一导电类型（n）的掺杂的半导体材料的提供半导体主体（1）与（1）相邻的该半导体主体的表面上，第二的掺杂的基极区（4），与第一导电型导电类型（p）互补，掩蔽所述半导体主体（1）的表面上，其特征在于，至少一个凹部（18）具有预定宽度被引入到掩模（16），从而使电阻区域至少部分地（4），其与所述第一导电类型的掺杂剂覆盖暴露的电阻区域（10），基极区的暴露（10）（N），使得表面侧的第一导电类型的暴露的电阻区域（10）（薄的沉积层（20） n）与高掺杂浓度形成，并且驱动在b 第一导电型（n）中的阻性区域（10）这样的掺杂剂elegten从具有高杂质浓度的薄沉积层（20），一个较厚的层（21，22）具有较低的掺杂浓度来形成。

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