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1. 发明申请

WO2016049594A1 TWO-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURE AND METHODS OF FABRICATION 审中-公开
标题翻译：双晶体SRAM半导体结构和制造方法
公开(公告)号：WO2016049594A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052488
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C11/00 , G11C11/411 , G11C11/419 , G11C11/34 , G11C7/12
CPC分类号： H01L27/1104 , G11C11/39 , G11C11/41 , G11C11/411 , H01L21/8229 , H01L21/8249 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1025 , H01L27/1027 , H01L27/11 , H01L27/1116 , H01L29/0649 , H01L29/0804 , H01L29/083 , H01L29/0847 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/66272 , H01L29/66386 , H01L29/732 , H01L29/742 , H01L29/7455
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
摘要翻译：基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法一起被描述。存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。标准CMOS工艺技术可用于制造SRAM。

2. 发明申请

WO2002101810A1 C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD 审中-公开
标题翻译：用于改进的信号双极晶体管输入的植入物
公开(公告)号：WO2002101810A1
公开(公告)日：2002-12-19
申请号：PCT/EP2002/006923
申请日：2002-06-04
申请人： INTERNATIONAL BUSINESS MACHINES , COMPANIE IBM FRANCE
发明人： COOLBAUGH, Douglas, D. , SCHONENBERG, Kathryn, T.
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.
摘要翻译：提供了一种改善SiGe双极性产率以及制造SiGe异质结双极晶体管的方法。本发明的方法包括将碳C离子注入到器件的以下区域之一：集电极区域（16），子集电极区域（14），非本征基极区域（29）和集电极基极结区域（27）。在优选实施例中，上述每个区域包括C植入物。

3. 发明申请

WO2014071294A1 ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION 审中-公开
标题翻译：具有隔离SCR的ESD保护电路用于负压运行
公开(公告)号：WO2014071294A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/068276
申请日：2013-11-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SALMAN, Akram, A. , FARBIZ, Farzan , CHATTERJEE, Amitava , WU, Xiaoju
IPC分类号： H01L29/66 , H02H9/00
CPC分类号： H01L27/0262 , H01L29/1012 , H01L29/7424 , H01L29/7436
摘要： A semiconductor controlled rectifier for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.
摘要翻译：公开了一种用于集成电路的半导体可控整流器。半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

4. 发明申请

WO2016049598A1 SIX-TRANSISTOR SRAM SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION 审中-公开
标题翻译：六极晶体管SRAM半导体结构和制造方法
公开(公告)号：WO2016049598A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052493
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie , CHEVALLIER, Christophe
IPC分类号： G11C7/00
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/41 , G11C11/411 , G11C11/412 , G11C11/419 , H01L21/76229 , H01L21/768 , H01L21/8229 , H01L21/8249 , H01L23/528 , H01L27/0623 , H01L27/0821 , H01L27/0826 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/0642 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1012 , H01L29/1095 , H01L29/42304 , H01L29/6625 , H01L29/66272 , H01L29/735 , H01L29/737 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricatingit. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
摘要翻译：基于用于SRAM集成电路的晶闸管的双晶体管存储单元与制造工艺一起被描述。存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。标准CMOS工艺技术可用于制造SRAM。

5. 发明申请

WO2015040202A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO2015040202A1
公开(公告)日：2015-03-26
申请号：PCT/EP2014/070082
申请日：2014-09-22
申请人： ABB TECHNOLOGY AG
发明人： BAUER, Friedhelm
IPC分类号： H01L29/745 , H01L29/749 , H01L29/06
CPC分类号： H01L29/7455 , H01L29/0649 , H01L29/0834 , H01L29/0839 , H01L29/0847 , H01L29/1012 , H01L29/1095 , H01L29/41716 , H01L29/749
摘要： A power semiconductor device (1) is provided comprising, in the following order: - a collector electrode (1), - a collector layer (2) of a second conductivity type, - a drift layer (3) of a first conductivity type, - a base layer (4) of the second conductivity type, - a first insulating layer (8) having an opening (82), - an emitter layer (5) of the first conductivity type, wherein the emitter layer (5) is in contact with the base layer (4) and separated from the drift layer (3) at least by one of the first insulating layer (8) or the base layer (4), - a body layer (6) of the second conductivity type arranged laterally to the emitter layer (5) and separated from the base layer (4) by the first insulating layer (8) and the emitter layer (5), - a source region (7) of the first conductivity type separated from the emitter layer (5) by the body layer (6), - an emitter electrode (15) contacted by the source region (7). The device further comprises a first layer (65) of the second conductivity type in contact with the emitter electrode (15) and separated from the base layer (4), and a second layer (55) of the first conductivity type arranged between the first layer (65) and the base layer (4) and separated from the emitter layer (5) and the source region (7). A planar MIS gate electrode (9) is arranged laterally from the emitter electrode (15), a corresponding MIS channel being formable between the source region (7), the body layer (6) and the emitter layer (5). A thyristor current path (120) extends between the emitter layer (5), the base layer (4) and the drift layer (3) through the opening (82), and a turn-off MIS channel (110) is formable below the planar MIS gate electrode (9) from the first layer (65), the second layer (55), the base layer (4) to the drift layer (3).
摘要翻译：提供一种功率半导体器件（1），其包括以下顺序： - 集电极（1）， - 第二导电类型的集电极层（2）， - 第一导电类型的漂移层（3） - 第二导电类型的基极层（4）， - 具有开口（82）的第一绝缘层（8）， - 第一导电类型的发射极层（5），其中发射极层（5）处于与基底层（4）接触并且至少由第一绝缘层（8）或基底层（4）中的一个与漂移层（3）分离， - 布置成第二导电类型的体层（6）横向到发射极层（5）并且通过第一绝缘层（8）和发射极层（5）与基极层（4）分离， - 与发射极层分离的第一导电类型的源极区域（7）（5）通过所述主体层（6）， - 与所述源极区域（7）接触的发射极（15）。该装置还包括与发射电极（15）接触并与基底层（4）分离的第二导电类型的第一层（65）和第一导电类型的第二层（55），其布置在第一层（65）和基底层（4），并与发射极层（5）和源极区域（7）分离。平面的MIS栅电极（9）从发射电极（15）侧向设置，相应的MIS通道可在源极区（7），主体层（6）和发射极层（5）之间形成。晶闸管电流路径（120）通过开口（82）在发射极层（5），基极层（4）和漂移层（3）之间延伸，并且关断MIS通道（110）可形成在从第一层（65），第二层（55），基底层（4）到漂移层（3）的平面MIS栅电极（9）。

6. 发明申请

WO2014140094A1 POWER SEMICONDUCTOR DEVICE AND CORRESPONDING MODULE 审中-公开
标题翻译：功率半导体器件和相应模块
公开(公告)号：WO2014140094A1
公开(公告)日：2014-09-18
申请号：PCT/EP2014/054830
申请日：2014-03-12
申请人： ABB TECHNOLOGY AG
发明人： RAHIMO, Munaf
IPC分类号： H01L29/745 , H01L29/749 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7395 , H01L27/0623 , H01L29/0696 , H01L29/0813 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1012 , H01L29/1016 , H01L29/102 , H01L29/1095 , H01L29/41708 , H01L29/7455 , H01L29/749
摘要： A power semiconductor device (1) of the emitter switched thyristor (EST) type comprising an emitter electrode (2) and a collector electrode (25) on opposite sides (22, 27) of a wafer (10), wherein a gate electrode (7) arranged on the emitter side (22) comprises a conductive gate layer (72) and an insulating layer (74), wherein layers are arranged in the following order between the collector and emitter sides (27, 22): a p doped collector layer (6), an n- doped drift layer (5), an n doped enhancement layer (52), a p doped base layer (4) with first and second base regions (42, 44), and n+ doped first and second emitter layers (3, 35), wherein the emitter electrode (2) contacts the first emitter layer (3) and the first base region (42), wherein the second emitter layer (35) is insulated from the emitter electrode (2) by the insulating layer (74) and wherein the second emitter layer (35) is separated from the first emitter layer (3) by the base layer (4), wherein the enhancement layer (52) is arranged between the first base region (42) and the drift layer (5), separates the first base region (42) from the second base region (44) and the drift layer (5) and contacts the second emitter layer (35), wherein an IGBT channel (100) is formable from the first emitter layer (3) via the first base region (42) to the drift layer (5), wherein a thyristor channel (120) is formable from the second emitter layer (35) via the second base region (44) to the drift layer (5), wherein a MOS channel (140) is formable from first emitter layer (3) via the first base region (42) to the second emitter layer (35).
摘要翻译：发射极开关晶闸管（EST）型的功率半导体器件（1）包括在晶片（10）的相对侧（22,27）上的发射极（2）和集电极（25），其中栅电极配置在发射极侧（22）上的电荷层（7,7）包括导电栅极层（72）和绝缘层（74），其中层在集电极和发射极侧（27,22）之间按照以下顺序排列：（6），n掺杂漂移层（5），n掺杂增强层（52），具有第一和第二基极区（42,44）的p掺杂基底层（4），以及n +掺杂的第一和第二发射极层（3,35），其中所述发射电极（2）接触所述第一发射极层（3）和所述第一基极区域（42），其中所述第二发射极层（35）通过绝缘体与所述发射极（2）绝缘层（74），并且其中所述第二发射极层（35）由所述基底层（4）与所述第一发射极层（3）分离，其中所述增强层（52）布置在第一基极区域（42）和漂移层（5）之间，将第一基极区域（42）与第二基极区域（44）和漂移层（5）分离并接触第二发射极层（35），其中IGBT通道（100）可以通过第一基极区（42）从第一发射极层（3）形成到漂移层（5），其中晶闸管通道（120）可从第二发射极层（35）形成）经由第二基极区（44）到漂移层（5），其中MOS沟道（140）可以经由第一基极区（42）从第一发射极层（3）形成到第二发射极层（35）。

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