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1. 发明申请

WO1995019044A1 FELT HAVING A DIELECTRICALLY ISOLATED GATE CONNECT 审中-公开
标题翻译：具有电绝缘隔离栅连接的电缆
公开(公告)号：WO1995019044A1
公开(公告)日：1995-07-13
申请号：PCT/US1994014977
申请日：1994-12-29
申请人： HONEYWELL INC.
发明人： HONEYWELL INC. , SWIRHUN, Stanley, E.
IPC分类号： H01L21/76
CPC分类号： H01L29/66462 , H01L21/7605 , H01L29/7786
摘要： A HIGHFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.
摘要翻译：具有栅极的HIGHFET，其具有通过电介质层与FET异质结构晶片隔离的焊盘，以最小化栅极和晶片之间的漏电流。该器件的制造方法包括仅在FET的有源区域上施加栅极金属，并在栅极金属上覆盖光刻胶。包括由光致抗蚀剂覆盖的区域的晶片被电介质层覆盖。与栅极金属上的电介质层一起除去光致抗蚀剂层。在预先存在的栅极金属上形成另一层栅极金属，该栅极金属包括在剩余电介质层的一部分上的栅极焊盘。

2. 发明申请

WO1989004554A1 P-TYPE BUFFER LAYERS FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路的P型缓冲层
公开(公告)号：WO1989004554A1
公开(公告)日：1989-05-18
申请号：PCT/US1988004014
申请日：1988-11-09
申请人： KOPIN CORPORATION
发明人： KOPIN CORPORATION , SALERNO, Jack, P. , LEE, Jhang, Woo , FAN, John, C., C.
IPC分类号： H01L29/10
CPC分类号： H01L21/7605 , H01L27/0605 , H01L29/1075
摘要： An integrated circuit having an epitaxial GaAs buffer layer containing p-type dopant is disclosed. The epitaxial p-doped buffer has a lower point defect/impurity density than bulk, melt-grown GaAs buffer layers and a lower carrier mobility than comparable n-doped buffer layers, and forms p-n junctions with n-doped regions of transistors resident on the buffer layer. The buffer substantially reduces interdevice and intradevice parasitic currents as well as sidegating and backgating. Furthermore, the p-doped epitaxial buffer enhances device isolation.
摘要翻译：公开了一种具有包含p型掺杂剂的外延GaAs缓冲层的集成电路。外延p掺杂缓冲液具有比本体，熔融生长的GaAs缓冲层低的点缺陷/杂质密度和比可比较的n掺杂缓冲层更低的载流子迁移率，并形成pn结与n = 缓冲层。该缓冲器基本上减少了设备间和入口内寄生电流，以及侧向和侧向。此外，p掺杂的外延缓冲器增强了器件隔离。

3. 发明申请

WO1985002496A1 METHOD OF FABRICATING AlGaAs SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS 审中-公开
标题翻译：制造具有高电阻率和低电阻率区域的AlGaAs半导体器件的方法
公开(公告)号：WO1985002496A1
公开(公告)日：1985-06-06
申请号：PCT/US1984001677
申请日：1984-10-18
申请人： AMERICAN TELEPHONE & TELEGRAPH COMPANY
发明人： AMERICAN TELEPHONE & TELEGRAPH COMPANY , FOCHT, Marlin, Wilbert , KOSZI, Louis, Alex , SCHWARTZ, Bertram
IPC分类号： H01L21/324
CPC分类号： H01L23/535 , H01L21/2654 , H01L21/266 , H01L21/3245 , H01L21/743 , H01L21/7605 , H01L21/8252 , H01L2924/0002 , Y10S148/084 , H01L2924/00
摘要： The property of materials in the GaAs/AlGaAs system, whereby at certain doses proton bombarded n-type material becomes highly resistive but p-type material remains highly conductive, is utilized to fabricate integrated circuits which include buried semiconductor interconnections or bus bars (14) between devices (D1, D2).

4. 发明申请

WO00060670A2 INTEGRATED SEMICONDUCTOR DEVICE WITH ONE LATERAL POWER GATE 审中-公开
标题翻译：有横向的执行单元集成的半导体器件
公开(公告)号：WO00060670A2
公开(公告)日：2000-10-12
申请号：PCT/DE2000/000812
申请日：2000-03-16
IPC分类号： H01L21/04 , H01L21/76 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/78 , H01L29/00
CPC分类号： H01L29/7816 , H01L21/7602 , H01L21/7605 , H01L29/0696 , H01L29/1083 , H01L29/1602 , H01L29/1608 , H01L29/20 , H01L29/66068
摘要： The invention relates to a semiconductor device (100) which contains a lateral power gate (50). Said power gate (50) is located within a semiconductor layer (20) that consists of a semiconductor material with an energy gap of at least 2 eV and that is laterally delimited by a trench (30) in the semiconductor layer (20). Said semiconductor layer (20) is arranged on a substrate (10) that has a higher thermal conductivity than silicon and that is electrically insulated vis-à-vis a substrate surface (11) that faces away from the semiconductor layer (20). The invention provides an integrated semiconductor device (100) for a high blocking voltage and a high frequency of operation.
摘要翻译：的半导体器件（100）包括一个横向功率元件（50）。功率元件（50）设置由具有由沟槽至少2 eV和侧的带隙的半导体材料构成的半导体层（20）（30）内，在半导体层（20）的限制。面对从基板表面（11）离开的基片（10）具有比硅更大的热导率在半导体层（20）和从该半导体层（20）中的一个设置的电是分离的。这导致一个高阻断电压和高开关频率一可组合的半导体装置（100）。

5. 发明申请

WO9939371A3 METHOD FOR PRODUCING A STRUCTURE SUCH AS AN INSULATOR SEMICONDUCTOR AND IN PARTICULAR SiCOI 审中-公开
标题翻译：用于生产绝缘体半导体和特殊SiCOI的结构的方法
公开(公告)号：WO9939371A3
公开(公告)日：1999-10-07
申请号：PCT/FR9900155
申请日：1999-01-27
申请人： COMMISSARIAT ENERGIE ATOMIQUE , CIOCCIO LEA DI
发明人： DI CIOCCIO LEA
IPC分类号： H01L21/02 , H01L21/04 , H01L21/76 , H01L21/762 , H01L21/84 , H01L27/12 , H01L21/20
CPC分类号： H01L21/7605 , H01L21/0475 , H01L21/7602 , H01L21/76254
摘要： The invention concerns a method for producing a structure comprising a support substrate (20) and a layer of semiconductor material (12) on one surface of the support substrate, the method consisting in: a) forming a semiconductor layer (12) on a surface of a first substrate (10); b) forming a cleavage zone in the first substrate, delimiting a surface layer (18); c) bringing the first substrate (10), with the semiconductor material (12), on the support substrate (20); d) supplying power to cleave the first substrate along the cleavage line (16); e) eliminating said surface layer (16) to expose the semiconductor material layer (12).
摘要翻译：本发明涉及一种用于制造结构的方法，该结构包括在支撑基板的一个表面上的支撑基板（20）和半导体材料层（12），该方法包括：a）在表面上形成半导体层（12）的第一衬底（10）; b）在第一衬底中形成切割区，限定表面层（18）; c）将带有半导体材料的第一衬底（10）带到支撑衬底（20）上; d）提供功率以沿着切割线（16）切割第一衬底; e）消除所述表面层（16）以露出半导体材料层（12）。

6. 发明申请

WO1995019043A1 FET HAVING MINIMIZED PARASITIC GATE CAPACITANCE 审中-公开
标题翻译：具有最小化的PARASITIC GATE电容的FET
公开(公告)号：WO1995019043A1
公开(公告)日：1995-07-13
申请号：PCT/US1994014976
申请日：1994-12-29
申请人： HONEYWELL INC.
发明人： HONEYWELL INC. , SWIRHUN, Stanley, E.
IPC分类号： H01L21/76
CPC分类号： H01L29/66462 , H01L21/7605 , H01L29/42316 , H01L29/7784 , Y10S148/105
摘要： A HIGFET having a gate pad situated over a non conducting portionof the channel layer of the heterostructure wafer. The method of producing this device involves appplication of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.
摘要翻译：一种HIGFET，其栅极焊盘位于异质结构晶片的沟道层的非导电部分之上。制造该器件的方法包括在晶片上施加非常薄的栅极金属层，以在进一步处理期间保护晶片表面。在FET的沟道层的有效区域上形成光致抗蚀剂涂层。对晶片施加离子隔离注入，导致沟道层的不被光致抗蚀剂层覆盖的非导电部分。去除光致抗蚀剂层，并且在栅极金属的薄层上施加厚的栅极金属层。栅极层被形成沟道层的非导电部分上的焊盘并且在沟道层的导电部分上方的至少一个手指，导致栅极具有最小化的寄生栅极电容。

7. 发明申请

WO1993011562A1 METHOD OF MAKING SEMICONDUCTOR COMPONENTS WITH ELECTROCHEMICAL RECOVERY OF THE SUBSTRATE 审中-公开
标题翻译：制造具有基板的电化学恢复的半导体元件的方法
公开(公告)号：WO1993011562A1
公开(公告)日：1993-06-10
申请号：PCT/FR1992001154
申请日：1992-12-04
申请人： PICOGICA S.A. , NUYEN, Linh, T.
发明人： PICOGICA S.A.
IPC分类号： H01L21/78
CPC分类号： H01L21/764 , H01L21/7605 , H01L21/76264 , H01L21/76275 , H01L21/76289
摘要： The method comprises the following steps: a) producing a semi-insulating or n-type substrate (1); (b) forming an intermediate layer (2) of a p+ doped material on the surface of the substrate; (c) forming an active layer (3) on this intermediate layer, comprising at least one n-doped lower layer; (d) forming a series of components (5) by etching and metallization of this active layer; (g) fixing a common support plate (8) on the assembly thus produced to secure the components mechanically, and; (h) dissolving the intermediate layer material by anodic means and without illumination, leaving intact the other materials so as to separate the substrate from the said components without dissolving it.

8. 发明申请

WO1982003946A1 METHOD OF FORMING WIDE BANDGAP REGION WITHIN A MULTILAYER III-V SEMICONDUCTORS 审中-公开
标题翻译：在多层III-V半导体中形成宽带区域的方法
公开(公告)号：WO1982003946A1
公开(公告)日：1982-11-11
申请号：PCT/US1982000574
申请日：1982-05-04
申请人： UNIV ILLINOIS
发明人： UNIV ILLINOIS , HOLONYAK NICK JR , LAIDIG WYN DAVIS
IPC分类号： H01L21/76
CPC分类号： H01S5/026 , H01L21/182 , H01L21/2654 , H01L21/26546 , H01L21/26586 , H01L21/7605 , H01S5/20 , H01S5/2059
摘要： Method for converting a multilayer semiconductor structure (20), that includes active semiconductor regions (22) interposed between semiconductor barrier layers (24), into a disordered alloy by selective introduction of a disordering Zn, Si or As elements or ions into the multilayer structure. The disordered alloy exhibits wider energy band-gap while still retaining single crystallinity. The process is illustratively used to make Schottky barrier field effect transistor (fig. 5), light emitting diode (fig. 3-4) and intergrated electro-optical device (fig. 6).
摘要翻译：通过选择性地将无序Zn，Si或As元素或离子引入到多层结构中，将包含介于半导体势垒层（24）之间的有源半导体区域（22））的多层半导体结构（20）转换为无序合金的方法。无序合金表现出更宽的能带隙，同时仍保持单一结晶度。该过程示例性地用于制造肖特基势垒场效应晶体管（图5），发光二极管（图3-4）和集成电光器件（图6））。

9. 发明申请

WO2016105437A1 HIGH MOBILITY NANOWIRE FIN CHANNEL ON SILICON SUBSTRATE FORMED USING SACRIFICIAL SUB-FIN 审中-公开
标题翻译：使用SACRIFICIAL SUB-FIN形成的硅基板上的高移动性NANOWIRE FIN通道
公开(公告)号：WO2016105437A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072448
申请日：2014-12-26
申请人： INTEL CORPORATION , DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
发明人： DEWEY, Gilbert , METZ, Matthew V. , KAVALIEROS, Jack T. , RACHMADY, Willy , GHANI, Tahir , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GARDNER, Sanaz K. , RADOSAVLJEVIC, Marko , GLASS, Glenn A.
IPC分类号： H01L21/762 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/30604 , H01L21/31111 , H01L21/7605 , H01L21/762 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/122 , H01L29/161 , H01L29/20 , H01L29/66469 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
摘要翻译：集成电路管芯包括用于晶体管（例如，作为MOS器件的沟道的单个材料或堆叠）的沟道材料的四栅极器件纳米线，其通过从沟道材料的下方去除一部分子鳍材料而形成，其中亚翅片材料在长宽比捕集（ART）沟槽中生长。在某些情况下，在形成这样的纳米线时，可以去除通道下的有缺陷的翅片材料或区域。这种去除隔离了翅片通道，去除了翅片缺陷和泄漏路径，并且形成具有四个暴露表面的通道材料的纳米线，栅极材料可以形成在其上。

10. 发明申请

WO2009101870A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2009101870A1
公开(公告)日：2009-08-20
申请号：PCT/JP2009/051700
申请日：2009-02-02
申请人：日本電気株式会社 , 田能村昌宏
发明人：田能村昌宏
IPC分类号： H01L21/338 , H01L21/28 , H01L21/74 , H01L21/76 , H01L27/095 , H01L29/06 , H01L29/778 , H01L29/812
CPC分类号： H01L21/8258 , H01L21/7605 , H01L21/8252 , H01L27/0605 , H01L29/2003 , H01L29/7787 , H01L29/802
摘要：　配線の断線やショートを生じずに、低コスト化と素子間の電気的絶縁を図ることができる半導体装置を提供する。　半導体素子、並びに、半導体素子の直下に存在する低抵抗層を、接地された貫通ビアで囲むため、半導体素子は電気的に遮蔽される。そのため、隣接素子間との電気的絶縁が可能になる。従って、再成長技術や溝を形成する必要が無いため、配線の断線やショートを生じずに、低コストで電気的絶縁が可能になる。
摘要翻译：提供了一种低成本的半导体器件，其中元件彼此电绝缘，而不会发生布线的断开和短路。由于半导体元件正下方存在的半导体元件和低电阻层被接地的通孔包围，所以半导体元件被电屏蔽。因此，半导体元件可以与相邻元件电绝缘。由于不需要再生技术和形成沟槽，所以以低成本提供电绝缘，而不会产生断线和布线短路。

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