专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2014003842A1 SHALLOW TRENCH ISOLATION STRUCTURES 审中-公开
标题翻译： SHOWOW TRENCH隔离结构
公开(公告)号：WO2014003842A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/030728
申请日：2013-03-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , CHENG, Kangguo , HARAN, Balasubramanian, S. , KHAKIFIROOZ, Ali , KULKARNI, Pranita , KUMAR, Arvind , PONOTH, Shom
发明人： DORIS, Bruce, B. , CHENG, Kangguo , HARAN, Balasubramanian, S. , KHAKIFIROOZ, Ali , KULKARNI, Pranita , KUMAR, Arvind , PONOTH, Shom
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
摘要翻译：提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

2. 发明申请

WO2011054664A1 MULTIPLE WIDTH FEATURES IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的多功能特性
公开(公告)号：WO2011054664A1
公开(公告)日：2011-05-12
申请号：PCT/EP2010/065715
申请日：2010-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , DORIS, Bruce , ZHANG, Ying , CHENG, Kangguo , HOLMES, Steven , HUA, Xuefeng
发明人： DORIS, Bruce , ZHANG, Ying , CHENG, Kangguo , HOLMES, Steven , HUA, Xuefeng
IPC分类号： H01L21/033 , H01L21/308 , H01L21/336
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

3. 发明申请

WO2009094282A1 TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL 审中-公开
标题翻译：使用自组装材料的二维图案
公开(公告)号：WO2009094282A1
公开(公告)日：2009-07-30
申请号：PCT/US2009/031044
申请日：2009-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DALTON, Timothy , DORIS, Bruce, B. , KIM, Ho-cheol , RADENS, Carl
发明人： DALTON, Timothy , DORIS, Bruce, B. , KIM, Ho-cheol , RADENS, Carl
IPC分类号： H01L21/3213
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure on a semiconductor substrate having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer (20). The first layer is filled with a filler material and a second layer (60) is deposited above the first layer (20) containing the first nanoscale nested line structure. A second nanoscale self-aligned self- assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer (60). The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer (12) beneath the first layer (20) to form an array of structures containing periodicity in two directions.
摘要翻译：在第一层（20）内由第一自组装嵌段共聚物形成具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的半导体衬底上的第一纳米级自对准自组装嵌套线结构。第一层填充有填充材料，并且第二层（60）沉积在包含第一纳米级嵌套线结构的第一层（20）上方。具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层（60）内的第二自组装嵌段共聚物形成。将第一纳米尺度嵌套线结构和第二纳米级嵌套线结构的复合图案转移到第一层（20）下面的下层（12）中以形成在两个方向上包含周期性的结构阵列。

4. 发明申请

WO2009019187A2 CIRCUIT STRUCTURE WITH METAL GATE AND HIGH-K DIELECTRIC 审中-公开
标题翻译：具有金属栅和高K电介质的电路结构
公开(公告)号：WO2009019187A2
公开(公告)日：2009-02-12
申请号：PCT/EP2008/060022
申请日：2008-07-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CARTIER, Eduard, Albert , NARAYANAN, Vijay , PARUCHURI, Vamsi , LINDER, Barry, Paul , DORIS, Bruce
发明人： CARTIER, Eduard, Albert , NARAYANAN, Vijay , PARUCHURI, Vamsi , LINDER, Barry, Paul , DORIS, Bruce
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.
摘要翻译：公开了具有高k介质栅极绝缘体和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层已经由单个公共金属层制造。由于单个普通金属，器件制造简化，需要减少数量的掩模。此外，作为使用单层金属作为两种类型的器件的栅极的进一步的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。通过选择普通金属材料和高k电介质的氧气曝光来调节器件阈值。阈值是针对低功耗设备操作的。

5. 发明申请

WO2006065759A3 DUAL STRESSED SOI SUBSTRATES 审中-公开
标题翻译：双应力SOI衬底
公开(公告)号：WO2006065759A3
公开(公告)日：2007-06-14
申请号：PCT/US2005044957
申请日：2005-12-13
申请人： IBM , CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
发明人： CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
IPC分类号： H01L21/84 , H01L27/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

6. 发明申请

WO2006115894A2 USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 审中-公开
标题翻译：使用金属/金属氮化物双层作为自对准的标准CMOS器件中的栅极电极
公开(公告)号：WO2006115894A2
公开(公告)日：2006-11-02
申请号：PCT/US2006014516
申请日：2006-04-18
申请人： IBM , CARTIER EDUARD A , COPEL MATTHEW W , DORIS BRUCE B , JAMMY RAJARAO , KIM YOUNG-HEE , LINDER BARRY P , NARAYANAN VIJAY , PARUCHURI VAMSI K , WONG KEITH KWONG HON
发明人： CARTIER EDUARD A , COPEL MATTHEW W , DORIS BRUCE B , JAMMY RAJARAO , KIM YOUNG-HEE , LINDER BARRY P , NARAYANAN VIJAY , PARUCHURI VAMSI K , WONG KEITH KWONG HON
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

7. 发明申请

WO2005124871A3 HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-GATE MOSFETS 审中-公开
公开(公告)号：WO2005124871A3
公开(公告)日：2005-12-29
申请号：PCT/US2005/021674
申请日：2005-06-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , IEONG, Meikei , NOWAK, Edward J. , YANG, Min
发明人： DORIS, Bruce, B. , IEONG, Meikei , NOWAK, Edward J. , YANG, Min
IPC分类号： H01L27/01 , H01L27/12
摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

8. 发明申请

WO2005064665A1 REDUCTION OF BORON DIFFUSIVITY IN pFETs 审中-公开
标题翻译：减少pFET中的BORON差异
公开(公告)号：WO2005064665A1
公开(公告)日：2005-07-14
申请号：PCT/US2003/039025
申请日：2003-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BUEHRER, Frederick, William , CHIDAMBARRAO, Dureseti , DORIS, Bruce, B. , HUANG, Hsiang-Jen , YANG, Haining
发明人： BUEHRER, Frederick, William , CHIDAMBARRAO, Dureseti , DORIS, Bruce, B. , HUANG, Hsiang-Jen , YANG, Haining
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译：应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率，从而改变最终的硼浓度和/或分布/梯度。在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

9. 发明申请

WO2005050701A3 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 审中-公开
公开(公告)号：WO2005050701A3
公开(公告)日：2005-06-02
申请号：PCT/US2004/037434
申请日：2004-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
发明人： DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
IPC分类号： H01L31/119
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

10. 发明申请

WO2013089853A1 METHOD AND STRUCTURE FOR FORMING ON-CHIP QUALITY CAPACITORS WITH ETSOI TRANSISTORS 审中-公开
标题翻译：用ETSOI晶体管形成片上质量电容器的方法和结构
公开(公告)号：WO2013089853A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/055037
申请日：2012-09-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , DORIS, Bruce, B. , KHAKIFIROOZ, Ali , SHAHIDI, Ghavam
发明人： CHENG, Kangguo , DORIS, Bruce, B. , KHAKIFIROOZ, Ali , SHAHIDI, Ghavam
IPC分类号： H01L27/04 , H01L29/78 , H01L29/93
CPC分类号： H01L27/1203 , H01L27/0629 , H01L27/105 , H01L27/10805 , H01L28/40 , H01L29/66181 , H01L29/94
摘要： An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中通过ETSOI和薄BOX层蚀刻，分别在其晶体管和电容器区域中形成ETSOI晶体管和电容器。电容器形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器或变容二极管。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式