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1. 发明申请

WO2012069798A1 DATA PROCESSING APPARATUS HAVING BIT FIELD MANIPULATION INSTRUCTION AND METHOD 审中-公开
标题翻译：具有位操作指令和方法的数据处理设备
公开(公告)号：WO2012069798A1
公开(公告)日：2012-05-31
申请号：PCT/GB2011/051841
申请日：2011-09-29
申请人： ARM LIMITED , SEAL, David James , GRISENTHWAITE, Richard Roy , STEPHENS, Nigel John
发明人： SEAL, David James , GRISENTHWAITE, Richard Roy , STEPHENS, Nigel John
IPC分类号： G06F9/30 , G06F7/76
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus (2) comprises a processing circuit (4) and instruction decoder (6). A bitfield manipulation instruction controls the processing apparatus (2) to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.
摘要翻译：数据处理装置（2）包括处理电路（4）和指令解码器（6）。位字段操作指令控制处理装置（2）从相应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。

2. 发明申请

WO2012120267A1 ADDRESS GENERATION IN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理设备中的地址生成
公开(公告)号：WO2012120267A1
公开(公告)日：2012-09-13
申请号：PCT/GB2012/050158
申请日：2012-01-26
申请人： ARM LIMITED , STEPHENS, Nigel John , SEAL, David James
发明人： STEPHENS, Nigel John , SEAL, David James
IPC分类号： G06F9/34 , G06F9/30 , G06F9/32 , G06F9/355
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译：提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址所述部分地址结果使用至少一个补充程序指令。部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。还提供了相应的数据处理方法，虚拟机和计算机程序产品。

3. 发明申请

WO2012049474A1 CONDITIONAL SELECTION OF DATA ELEMENTS 审中-公开
标题翻译：条件选择数据元素
公开(公告)号：WO2012049474A1
公开(公告)日：2012-04-19
申请号：PCT/GB2011/051847
申请日：2011-09-29
申请人： ARM LIMITED , CRASKE, Simon John , GRISENTHWAITE, Richard Roy , STEPHENS, Nigel John
发明人： CRASKE, Simon John , GRISENTHWAITE, Richard Roy , STEPHENS, Nigel John
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30072 , G06F9/30094 , G06F9/3842
摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register; a data processor configured to perform data processing operations controlled by the instruction decoder wherein: the data processor is responsive to the decoded at least one conditional select instruction and the condition having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register; and the data processor is responsive to the decoded at least one conditional select instruction and the condition not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
摘要翻译：一种数据处理装置，方法和计算机程序，其对诸如寄存器的一个数据元素执行操作，然后有条件地选择该寄存器或其上没有进行任何操作的另外的寄存器。该装置包括指令解码器，其被配置为对至少一个条件选择指令进行解码，所述至少一个条件选择指令指定主源寄存器，次源寄存器，目的地寄存器，条件以及对数据执行的操作来自次级源寄存器的元件; 配置为执行由指令解码器控制的数据处理操作的数据处理器，其中：数据处理器响应于解码的至少一个条件选择指令和具有预定结果的条件，以从次级源寄存器对数据元素执行操作以形成结果数据元素并将结果数据元素存储在目的寄存器中; 并且数据处理器响应于解码的至少一个条件选择指令和不具有预定结果的条件，以从主寄存器的数据元素形成结果数据元素，并将结果数据元素存储在目的寄存器中。

4. 发明申请

WO2021023954A1 DATA STRUCTURE PROCESSING 审中-公开
公开(公告)号：WO2021023954A1
公开(公告)日：2021-02-11
申请号：PCT/GB2020/050774
申请日：2020-03-23
申请人： ARM LIMITED
发明人： STEPHENS, Nigel John , MANSELL, David Hennah , GRISENTHWAITE, Richard Roy , EVANS, Matthew Lucien
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address- indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.

5. 发明申请

WO2018154273A1 ELEMENT BY VECTOR OPERATIONS IN A DATA PROCESSING APPARATUS 审中-公开
公开(公告)号：WO2018154273A1
公开(公告)日：2018-08-30
申请号：PCT/GB2018/050311
申请日：2018-02-02
申请人： ARM LIMITED
发明人： MAGKLIS, Grigorios , STEPHENS, Nigel John , EAPEN, Jacob , EYOLE, Mbou , MANSELL, David Hennah
IPC分类号： G06F9/30
摘要： A data processing apparatus, a method of operating a data processing apparatus, a non-transitory computer readable storage medium, and an instruction are provided. The instruction specifies a first source register, a second source register, and an index. In response to the instruction control signals are generated, causing processing circuitry to perform a data processing operation with respect to each data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation. Each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of the data group, and each data group comprises a plurality of data elements. The operands of the data processing operation for each data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. A technique for element-by-vector operation which is readily scalable as the register width grows.

6. 发明申请

WO2017064456A1 MOVE PREFIX INSTRUCTION 审中-公开
标题翻译：移动前缀说明
公开(公告)号：WO2017064456A1
公开(公告)日：2017-04-20
申请号：PCT/GB2016/052838
申请日：2016-09-14
申请人： ARM LIMITED
发明人： GRISENTHWAITE, Richard Roy , STEPHENS, Nigel John
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3017
摘要： An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.
摘要翻译：装置2具有指令融合电路50，用于融合从数据存储器取出的两个或更多指令以生成要由处理电路14处理的融合指令。提供移动前缀指令，其向指令融合电路50可以将移动前缀指令与紧随其后的数据处理指令融合，而不需要比较移动前缀指令和紧随其后的指令指定的寄存器。这使得指令熔合电路50能够以降低的硬件和能量成本来实现。

7. 发明申请

WO2022023701A1 REGISTER ADDRESSING INFORMATION FOR DATA TRANSFER INSTRUCTION 审中-公开
公开(公告)号：WO2022023701A1
公开(公告)日：2022-02-03
申请号：PCT/GB2021/051704
申请日：2021-07-05
申请人： ARM LIMITED
发明人： STEPHENS, Nigel John , MILANOVIC, Jelena , MANSELL, David Hennah
IPC分类号： G06F9/30
摘要： A data transfer instruction is provided which specifies register addressing information for identifying a target portion of the register storage. In response to the data transfer instruction, instruction decoding circuitry 30 controls processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage. The register addressing information includes at least: a base register identifier identifying a base register of the register storage for storing a base value; and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage. This can be useful to provide an instruction set architecture which supports code that is scalable to variable data structure sizes, and which supports loop unrolling.

8. 发明申请

WO2020161470A1 ANCHORED DATA ELEMENT CONVERSION 审中-公开
公开(公告)号：WO2020161470A1
公开(公告)日：2020-08-13
申请号：PCT/GB2020/050219
申请日：2020-01-30
申请人： ARM LIMITED
发明人： LUTZ, David Raymond , BURGESS, Neil , HINDS, Christopher Neal , STEPHENS, Nigel John
IPC分类号： H03M7/24 , G06F9/30
摘要： An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

9. 发明申请

WO2019011653A1 TESTING BIT VALUES INSIDE VECTOR ELEMENTS 审中-公开
公开(公告)号：WO2019011653A1
公开(公告)日：2019-01-17
申请号：PCT/EP2018/067234
申请日：2018-06-27
申请人： ARM LIMITED
发明人： MAGKLIS, Grigorios , STEPHENS, Nigel John
IPC分类号： G06F9/30
摘要： An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

10. 发明申请

WO2019115142A1 VECTOR ADD-WITH-CARRY INSTRUCTION 审中-公开
公开(公告)号：WO2019115142A1
公开(公告)日：2019-06-20
申请号：PCT/EP2018/081444
申请日：2018-11-15
申请人： ARM LIMITED
发明人： EYOLE, Mbou , STEPHENS, Nigel John , BURGESS, Neil , MAGKLIS, Grigorios
IPC分类号： G06F9/30
摘要： Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

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