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1. 发明申请

WO2018134056A1 TEST PENDING EXTERNAL INTERRUPTION INSTRUCTION 审中-公开
公开(公告)号：WO2018134056A1
公开(公告)日：2018-07-26
申请号：PCT/EP2018/050180
申请日：2018-01-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GREINER, Dan , SLEGAL, Timothy , KUBALA, Jeffrey, Paul , FARRELL, Mark , MULDER, James
IPC分类号： G06F9/30
摘要： Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.

2. 发明申请

WO2016066486A1 CONTROLLING EXECUTION OF THREADS IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：控制在多线程处理器中的线程执行
公开(公告)号：WO2016066486A1
公开(公告)日：2016-05-06
申请号：PCT/EP2015/074332
申请日：2015-10-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： SLEGEL, Timothy , ALEXANDER, Khary, Jason , BUSABA, Fadi, Yusuf , FARRELL, Mark , RELL JR, John, Gilbert
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F8/314 , G06F8/45 , G06F8/456 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3851
摘要： Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.
摘要翻译：控制处理器内核中线程的执行。处理器核心支持同时多线程（SMT），从而可以有效地在同一物理处理器硬件上同时操作多个逻辑中央处理单元（CPU）。这些逻辑CPU中的每一个被认为是线程。在这种多线程环境中，可能希望一个线程阻止处理器核心上的其他线程执行。这可能是响应于运行需要处理器核心资源的关键序列或其他序列，或者以其他线程将干扰其执行的方式来操纵处理器核心资源。

3. 发明申请

WO2015144479A1 ADDRESS EXPANSION AND CONTRACTION IN A MULTITHREADING COMPUTER SYSTEM 审中-公开
标题翻译：在多计算机系统中的地址扩展和承包
公开(公告)号：WO2015144479A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/055447
申请日：2015-03-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GREINER, Dan , FARRELL, Mark , OSISEK, Damian, Leo , SCHMIDT, Donald, William , BUSABA, Fadi, Yusuf , KUBALA, Jeffrey, Paul , BRADBURY, Jonathan, David , HELLER, Lisa, Cranton , SLEGEL, Timothy
IPC分类号： G06F9/50 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/5077
摘要： A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.
摘要翻译：计算机系统包括具有可在单线程（ST）模式和多线程（MT））模式之间配置的核心的配置。 ST模式寻址主线程，MT模式寻址主线程和核心共享资源上的一个或多个辅助线程。多线程设施被配置为控制配置的利用以执行包括使用核心地址值以及从ST模式切换到MT模式在ST模式下访问主线程的方法。主线程或一个或多个次线程中的一个线程使用扩展的地址值以MT模式访问，其中扩展的地址值包括与线程地址值连接的核心地址值。

4. 发明申请

WO2015144422A1 EXITING MULTIPLE THREADS IN A COMPUTER 审中-公开
标题翻译：在计算机中排除多个螺纹
公开(公告)号：WO2015144422A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/054741
申请日：2015-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： HELLER, Lisa, Cranton , BUSABA, Fadi, Yusuf , FARRELL, Mark
IPC分类号： G06F9/48
CPC分类号： G06F9/45558 , G06F9/485 , G06F2009/45575
摘要： According to one aspect, a computer system includes a configuration with a machine enabled to operate in a single thread (ST) mode and a multithreading (MT) mode. In addition, the machine includes physical threads. The machine is configured to perform a method that includes executing a guest entity on the core in MT mode. The guest entity includes all or a portion of a guest VM, and a plurality of logical threads executing on the physical threads. An exit event is detected at the machine. Based on detecting the exit event, the machine waits until all of the logical threads that are currently executing on the physical threads have reached a synchronization point. A state that includes exit reason information is saved for each of the logical threads and the execution of a host is initiated in the ST mode on one of the physical threads.
摘要翻译：根据一个方面，计算机系统包括具有能够以单线程（ST）模式和多线程（MT））模式操作的机器的配置。另外，机器包括物理线程。机器被配置为执行包括以MT模式在核心上执行客体实体的方法。客体实体包括客户VM的全部或一部分，以及在物理线程上执行的多个逻辑线程。在机器处检测到出口事件。基于检测退出事件，机器等待直到当前在物理线程上执行的所有逻辑线程已达到同步点。为每个逻辑线程保存包括退出原因信息的状态，并且在物理线程之一上以ST模式启动主机的执行。

5. 发明申请

WO2013108092A1 PROVIDING BY ONE PROGRAM TO ANOTHER PROGRAM ACCESS TO A WARNING TRACK FACILITY 审中-公开
标题翻译：通过一个程序提供给另一个程序访问警告跟踪设施
公开(公告)号：WO2013108092A1
公开(公告)日：2013-07-25
申请号：PCT/IB2012/056372
申请日：2012-11-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GAINEY JR, Charles , KUBALA, Jeffrey, Paul , FARRELL, Mark , SCHMIDT, Donald, William , PIERCE, Bernard , ROGERS, Robert , MULDER, James
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F9/45558 , G06F9/4887 , G06F9/5038 , G06F2009/45579
摘要： A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
摘要翻译：提供程序（例如，操作系统）警告其具有执行诸如清理（例如，完成，停止和/或移动可分派单元）的功能的宽限期。在一个示例中，该程序正在被警告，它正在失去对其共享资源的访问。例如，在虚拟环境中，客户程序被警告，即将要丢失其中央处理单元的资源，因此它将执行诸如清理的功能。

6. 发明申请

WO2009087232A2 COMPUTER CONFIGURATION VIRTUAL TOPOLOGY DISCOVERY 审中-公开
标题翻译：计算机配置虚拟拓扑发现
公开(公告)号：WO2009087232A2
公开(公告)日：2009-07-16
申请号：PCT/EP2009/050250
申请日：2009-01-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GAINEY JR., Charles , FARRELL, Mark , KUBALA, Jeffrey , SCHMIDT, Donald
发明人： GAINEY JR., Charles , FARRELL, Mark , KUBALA, Jeffrey , SCHMIDT, Donald
IPC分类号： G06F9/50
CPC分类号： H04L41/12 , G06F9/30003 , G06F9/45545 , G06F9/45558 , G06F9/5077 , G06F2009/45566
摘要： In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
摘要翻译：在包括主处理器（主机CPU）的逻辑分区的主计算机系统中，用于发现客户配置的一个或多个客户处理器（客户CPU）的拓扑的设施和指令包括访客配置的访客处理器，其提取和执行存储系统获取计算机配置的拓扑信息的信息指令。所述拓扑信息包括所述配置的处理器的嵌套信息和主处理器向对应的客户处理器提供的奉献程度。该信息优选地存储在存储器中的单个表中。

7. 发明申请

WO2020156926A1 GENERAL-PURPOSE PROCESSOR INSTRUCTION TO PERFORM COMPRESSION/DECOMPRESSION OPERATIONS 审中-公开
公开(公告)号：WO2020156926A1
公开(公告)日：2020-08-06
申请号：PCT/EP2020/051658
申请日：2020-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GIAMEI, Bruce, Conrad , KLEIN, Matthias , SLEGEL, Timothy , FARRELL, Mark , SOFIA, Anthony, Thomas , WEISHAUPT, Simon , MISHRA, Ashutosh
IPC分类号： G06F9/30
摘要： A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general- purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performedby the instruction being a compression functionor a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.

8. 发明申请

WO2015144477A1 THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM 审中-公开
标题翻译：在多计算机系统中的线程上下文恢复
公开(公告)号：WO2015144477A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/055444
申请日：2015-03-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GREINER, Dan , FARRELL, Mark , OSISEK, Damian, Leo , SCHMIDT, Donald, William , BUSABA, Fadi, Yusuf , KUBALA, Jeffrey, Paul , BRADBURY, Jonathan, David , HELLER, Lisa, Cranton , SLEGEL, Timothy
IPC分类号： G06F9/46
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3851 , G06F9/461
摘要： THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM Amultithreading computer system includesa configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.
摘要翻译：多线程计算机系统中的线程上下文恢复延续计算机系统包括具有可在单线程（ST）模式和多线程（MT））模式之间配置的内核的配置。 ST模式寻址主线程，MT模式寻址主线程和核心共享资源上的一个或多个辅助线程。多线程设备被配置为控制配置的利用以执行包括基于从MT模式切换到ST模式的一个或多个次要线程的禁用方法。辅助线程的线程上下文不可用于程序。基于指定MT的最后一个程序指定的最大线程ID，通过以下步骤获得线程上下文：a）执行设置的MT指令以恢复MT模式，以及b）基于恢复的MT模式，访问该线程上下文。

9. 发明申请

WO2020156927A1 COMPRESSION/DECOMPRESSION INSTRUCTION SPECIFYING A HISTORY BUFFER TO BE USED IN THE COMPRESSION/DECOMPRESSION OF DATA 审中-公开
公开(公告)号：WO2020156927A1
公开(公告)日：2020-08-06
申请号：PCT/EP2020/051666
申请日：2020-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GIAMEI, Bruce, Conrad , SOFIA, Anthony, Thomas , KLEIN, Matthias , WEISHAUPT, Simon , FARRELL, Mark , SLEGEL, Timothy , MISHRA, Ashutosh , JACOBI, Christian
IPC分类号： G06F9/30
摘要： An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

10. 发明申请

WO2016066487A1 INSTRUCTIONS CONTROLLING ACCESS TO SHARED REGISTERS OF A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：控制访问多线程处理器的共享寄存器的指令
公开(公告)号：WO2016066487A1
公开(公告)日：2016-05-06
申请号：PCT/EP2015/074335
申请日：2015-10-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： SLEGEL, Timothy , BIRAN, Giora , BUSABA, Fadi, Yusuf , EREZ, Ophir , MESH, Alexander , FARRELL, Mark , HELLER, Lisa , JACOBI, Christian
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/30029 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/3012 , G06F9/3851 , G06F9/46 , G06F2209/521
摘要： Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.
摘要翻译：原子指令，包括比较和交换寄存器，加载和和寄存器以及加载和OR寄存器指令，使用寄存器而不是存储来在多线程处理器中通信和共享信息。这些寄存器可以访问多线程处理器的多个线程，并且指令在这些共享寄存器上运行。共享寄存器的访问由指令通过互锁控制。

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