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1. 发明申请

WO2012145578A1 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145578A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034367
申请日：2012-04-20
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/177
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

2. 发明申请

WO2012145511A2 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145511A2
公开(公告)日：2012-10-26
申请号：PCT/US2012/034250
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/173
CPC分类号： H03K19/17708 , G06F15/7867
摘要： An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.
摘要翻译：根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。在一些实施例中，多个外围设备包括至少一个可配置逻辑单元外围设备，其具有比集成电路设备上的输入 - 输出连接更多的输入。在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

3. 发明申请

WO2012145508A1 A LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH 审中-公开
标题翻译：用于将各种中断源组合成单个中断源和各种信号源以控制驱动强度的逻辑设备
公开(公告)号：WO2012145508A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034245
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/177
CPC分类号： H03K19/17712 , H03K19/17708
摘要： A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.
摘要翻译：处理器包括RISC CPU内核和包括可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为将多个输入组合成单个输出。可配置逻辑单元可以被编程为用作多个预定逻辑功能之一。

4. 发明申请

WO2012145511A3 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145511A3
公开(公告)日：2013-02-14
申请号：PCT/US2012034250
申请日：2012-04-19
申请人： MICROCHIP TECH INC , KILZER KEVIN LEE , STEEDMAN SEAN , ZDENEK JERROLD S , DELPORT VIVIEN , LUNDSTRUM ZEKE , DUVENHAGE FANIE
发明人： KILZER KEVIN LEE , STEEDMAN SEAN , ZDENEK JERROLD S , DELPORT VIVIEN , LUNDSTRUM ZEKE , DUVENHAGE FANIE
IPC分类号： G06F15/78
CPC分类号： H03K19/17708 , G06F15/7867
摘要： An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.
摘要翻译：根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。在一些实施例中，多个外围设备包括具有比集成电路设备上的输入 - 输出连接更多的输入的至少一个可配置逻辑单元外围设备。在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

5. 发明申请

WO2010042361A3 PROGRAMMABLE INTEGRATED CIRCUIT DEVICE TO SUPPORT INDUCTIVE SENSING 审中-公开
标题翻译：可编程集成电路设备支持感应感应
公开(公告)号：WO2010042361A3
公开(公告)日：2010-09-02
申请号：PCT/US2009058979
申请日：2009-09-30
申请人： MICROCHIP TECH INC , STEEDMAN SEAN , CURTIS KEITH E , RUSCU RADU , POP PETRU CRISTIAN
发明人： STEEDMAN SEAN , CURTIS KEITH E , RUSCU RADU , POP PETRU CRISTIAN
IPC分类号： H03K17/96
CPC分类号： H03K17/96 , H03K2217/96038
摘要： An integrated circuit device inductive touch analog front end excites selected ones of a plurality of inductive touch sensors and provides analog output signals representative of voltages across the coils of the plurality of inductive touch sensors. Various characteristics of the inductive touch analog front end are programmable, A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. The digital processor may program the characteristics of the inductive touch analog front end. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).
摘要翻译：集成电路器件感应触摸模拟前端激励多个感应触摸传感器中的选定的一个，提供表示多个感应触摸传感器的线圈两端的电压的模拟输出信号。感应式触摸模拟前端的各种特性是可编程的，A数字处理器控制多个感应式触摸传感器中的每一个的选择，并从感应触摸AFE接收相应的模拟输出电压信号。数字处理器可以对感应式模拟前端的特性进行编程。当由数字处理器确定线圈电压的充分变化时，假定该感应式触摸传感器已被致动，并且数字处理器基于多个感应式触摸传感器中的哪一个被触发（触摸）而采取行动。

6. 发明申请

WO2010093661A2 MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS 审中-公开
标题翻译：具有特殊银行指示的微控制器
公开(公告)号：WO2010093661A2
公开(公告)日：2010-08-19
申请号：PCT/US2010/023706
申请日：2010-02-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
发明人： LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
摘要翻译：一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块，没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

7. 发明申请

WO2012145505A1 SELECTING FOUR SIGNALS FROM SIXTEEN INPUTS 审中-公开
标题翻译：从第六代输入选择四个信号
公开(公告)号：WO2012145505A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034242
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/173
CPC分类号： H03K19/1737 , H03K19/17744
摘要： An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to I multiplexer.
摘要翻译：一种用于从设备中的多个y信号中选择多个输入信号的装置具有具有多个n至1个多路复用器的交换矩阵，其中每个n至1多路复用器被分配给y个信号的n个的不同输入集合其中n到1个复用器中的每一个的每组输入信号的小于n个输入信号的子集也是另一个n到I多路复用器的输入信号的子集。

8. 发明申请

WO2010042361A2 PROGRAMMABLE INTEGRATED CIRCUIT DEVICE TO SUPPORT INDUCTIVE SENSING 审中-公开
标题翻译：可编程集成电路设备，以支持感应传感
公开(公告)号：WO2010042361A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/058979
申请日：2009-09-30
申请人： MICROCHIP TECHNOLOGY INCORPORATED , STEEDMAN, Sean , CURTIS, Keith, E. , RUSCU, Radu , POP, Petru, Cristian
发明人： STEEDMAN, Sean , CURTIS, Keith, E. , RUSCU, Radu , POP, Petru, Cristian
IPC分类号： H03K17/96
CPC分类号： H03K17/96 , H03K2217/96038
摘要： An integrated circuit device inductive touch analog front end excites selected ones of a plurality of inductive touch sensors and provides analog output signals representative of voltages across the coils of the plurality of inductive touch sensors. Various characteristics of the inductive touch analog front end are programmable, A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. The digital processor may program the characteristics of the inductive touch analog front end. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).
摘要翻译：集成电路器件电感触摸模拟前端激励多个电感式触摸传感器中的选定电感式触摸传感器，并提供表示跨多个电感式触摸传感器的线圈的电压的模拟输出信号。电感式触摸模拟前端的各种特性是可编程的。数字处理器控制对多个电感式触摸传感器中的每一个的选择并且从电感式触摸AFE接收相应的模拟输出电压信号。数字处理器可以编程感应触摸模拟前端的特性。当数字处理器确定线圈电压的充分变化时，假定该电感触摸传感器已被启动，并且数字处理器基于多个电感触摸传感器中的哪一个被启动（触摸）而采取动作。 p>

9. 发明申请

WO2008137707A1 REGULATOR BYPASS START-UP IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：集成电路设备中的调节器旁路启动
公开(公告)号：WO2008137707A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062455
申请日：2008-05-02
申请人： MICROCHIP TECHNOLOGY INCORPORATED , STEEDMAN, Sean , DELPORT, Vivien , ZDENEK, Jerrold, S. , LOURENS, Ruan , CHARLES, Michael , JULICHER, Joseph , SCHROEDER, Eric
发明人： STEEDMAN, Sean , DELPORT, Vivien , ZDENEK, Jerrold, S. , LOURENS, Ruan , CHARLES, Michael , JULICHER, Joseph , SCHROEDER, Eric
IPC分类号： G11C5/14 , G05F1/46
CPC分类号： G11C5/147
摘要： An internal' voltage regulator (108) in an integrated circuit device (102) is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator (108) protects the low voltage core logic circuits (104, 106) of the integrated circuit device (102) from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory (104) may be part of and operational with the low voltage core logic circuits (104, 106) for storing device operating parameters. Therefore, the internal voltage regulator (108) also protects the low voltage nonvolatile memory (104) from excessive high voltages. Once the integrated circuit device (102) has stabilized and all logic circuits therein fully function, a bit(s) in the nonvolatile memory (104) may be read to determine if the internal voltage regulator (108) should remain active, e.g., power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device (102) is powered by a low voltage.
摘要翻译：在初始启动和/或上电复位操作时，集成电路器件（102）中的内部“稳压器（108）”总是有效。内部电压调节器（108）保护集成电路器件（102）的低电压核心逻辑电路（104,106）免受可能存在于特定应用中的过高的电压。此外，非易失性存储器（104）可以是用于存储设备操作参数的低电压核心逻辑电路（104,106）的一部分并且可操作。因此，内部稳压器（108）也保护低压非易失性存储器（104）免受过高的高电压的影响。一旦集成电路器件（102）已经稳定并且其中的所有逻辑电路完全起作用，则可以读取非易失性存储器（104）中的位以确定内部稳压器（108）是否应该保持有效，例如功率当集成电路器件（102）由低电压供电时，用高电压源操作或被置于旁路模式以进行低功率操作。

10. 发明申请

WO2010093657A3 MICROCONTROLLER WITH LINEAR MEMORY IN A BANKED MEMORY 审中-公开
标题翻译：带有线性内存的微控制器在一个银行存储器中
公开(公告)号：WO2010093657A3
公开(公告)日：2010-11-18
申请号：PCT/US2010023701
申请日：2010-02-10
申请人： MICROCHIP TECH INC , LUNDSTRUM ZEKE R , DELPORT VIVIEN , STEEDMAN SEAN , JULICHER JOSEPH
发明人： LUNDSTRUM ZEKE R , DELPORT VIVIEN , STEEDMAN SEAN , JULICHER JOSEPH
IPC分类号： G06F9/30 , G06F9/318 , G06F9/35 , G06F12/06
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.
摘要翻译：微控制器具有被分成多个存储体的数据存储器，用于向数据存储器提供地址的地址多路复用器，向地址多路复用器的第一输入提供第一部分地址的指令寄存器，不是存储体选择寄存器映射到数据存储器，用于向地址多路复用器的第一输入提供第二部分地址;以及多个特殊功能寄存器，映射到数据存储器，其中多个特殊功能寄存器包括间接访问寄存器，与第二输入所述地址多路复用器，并且其中所述数据存储器包括所述多个存储体中的多于一个存储体，所述多个存储体形成线性数据存储器块，其中没有特殊功能寄存器被映射到所述线性数据存储器块。

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