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1. 发明申请

WO2008055272A2 INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY 审中-公开
标题翻译：集成对称和非对称内存的数据
公开(公告)号：WO2008055272A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083671
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.
摘要翻译：存储在主存储器的对称和非对称存储器组件中的数据通过将第一数据识别为具有适合于存储在非对称存储器组件中的访问特性而被集成。第一个数据包含在要写入非对称内存组件的数据集合中。在要写入不对称存储器组件的数据集合内识别出一定数量的数据。在数据集合内将数据量与容量阈值进行比较，以确定对非对称存储器组件的块写入是否通过数据量来证明合理。如果证明合理，数据收集将加载到非对称内存组件。

2. 发明申请

WO2008055271A2 SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY 审中-公开
标题翻译：无缝应用访问混合主存储器
公开(公告)号：WO2008055271A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083669
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

3. 发明申请

WO2008055270A2 WRITING TO ASYMMETRIC MEMORY 审中-公开
标题翻译：写入非对称记忆
公开(公告)号：WO2008055270A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083668
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.
摘要翻译：存储器控制器写入与驻留在计算机系统内的主存储器的不对称存储器组件内并且具有对称存储器组件的数据相关联的虚拟地址，同时保留驻留在不对称内存组件。计算机系统的主存储器中的对称存储器组件被配置为启用随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块期间其他地址的可用性该地址的写作。非对称存储器组件被配置为启用块写入操作，其中在涉及地址的块写入操作期间，写入到非对称存储器组件的区域内的地址影响非对称存储器组件的区域内的其他地址的可用性。 p>

4. 发明申请

WO2008055269A2 ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY 审中-公开
标题翻译：混合主存储器中的不对称存储器迁移
公开(公告)号：WO2008055269A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083666
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
摘要翻译：通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来管理主存储器。存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件中的一个，并且访问指示如何与虚拟地址相关联的数据被访问的存储器使用特性。存储器控制器确定与虚拟地址具有适合于主存储器的非对称存储器组件的访问特征，并将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。在加载和使用存储器管理单元之后，从应用程序接收到用于读取与虚拟地址相关联的数据的命令，并且从非对称存储器组件检索与虚拟地址相关联的数据。

5. 发明申请

WO2008040028A3 SYSTEMS, METHODS, AND APPARATUS WITH PROGRAMMABLE MEMORY CONTROL FOR HETEROGENEOUS MAIN MEMORY 审中-公开
公开(公告)号：WO2008040028A3
公开(公告)日：2008-04-03
申请号：PCT/US2007/080015
申请日：2007-09-28
申请人： VIRIDENT SYSTEMS, INC. , OKIN, Kenneth , MOUSSA, George , GANAPATHY, Kumar , KARAMCHETI, Vijay , PAREKH, Rajesh
发明人： OKIN, Kenneth , MOUSSA, George , GANAPATHY, Kumar , KARAMCHETI, Vijay , PAREKH, Rajesh
IPC分类号： G06F12/00 , G06F13/00
摘要： A computer system is disclosed including a printed circuit board (200) (PCB) including a plurality of traces (116A.116B.116N)1 at least one processor (231) mounted to the PCB to couple to some of the plurality of trace (116A,116B,116N), a heterogeneous memory channel (125A.125N) including a plurality of sockets (113A.213A coupled to a memory channel bus of the PCB, and a memory controller (221) coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality o sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules (115A, 214A). The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

6. 发明申请

WO2008039886A2 MAIN MEMORY IN A SYSTEM WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO NON-VOLATILE MEMORY, AND RELATED TECHNOLOGIES 审中-公开
标题翻译：具有配置为控制非易失性存储器和相关技术的存储器控制器的系统中的主存储器
公开(公告)号：WO2008039886A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/079622
申请日：2007-09-27
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , GANAPATHY, Kumar , OKIN, Kenneth , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , GANAPATHY, Kumar , OKIN, Kenneth , PAREKH, Rajesh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G06F13/12 , G06F13/1657 , G06F13/1694 , G06F2212/25 , G06F2212/7203 , G11C7/1006 , G11C7/1072 , Y02D10/14
摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
摘要翻译：一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在与多个印刷电路板迹线中的一个或多个印刷电路板迹线耦合的印刷电路板上的存储器控制器，多个非易失型存储器集成电路耦合到印刷电路板，以及耦合在存储器控制器和多个非易失性类型的存储器集成电路之间的多个支持集成电路。

7. 发明申请

WO2008039885A2 SYSTEMS, METHODS, AND APPARATUS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES, AND RELATED TECHNOLOGIES 审中-公开
标题翻译：具有非易失型存储器模块的主存储器的系统，方法和装置及相关技术
公开(公告)号：WO2008039885A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/079619
申请日：2007-09-27
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , GANAPATHY, Kumar , OKIN, Kenneth , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , GANAPATHY, Kumar , OKIN, Kenneth , PAREKH, Rajesh
IPC分类号： G06F12/02
CPC分类号： G06F13/1657 , Y02D10/14
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non- volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

8. 发明申请

WO2009102821A2 METHODS AND APPARATUS FOR TWO-DIMENSIONAL MAIN MEMORY 审中-公开
标题翻译：用于二维主存储器的方法和设备
公开(公告)号：WO2009102821A2
公开(公告)日：2009-08-20
申请号：PCT/US2009/033843
申请日：2009-02-11
申请人： VIRIDENT SYSTEMS, INC.
发明人： KARAMCHETI, Vijay , GANAPATHY, Kumar
IPC分类号： G06F12/00 , G11C5/14 , G06F9/34 , G11C7/00
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从属存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收的地址而选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个存储器集成电路，以从存储器集成电路中的选定存储器位置读取数据或向其写入数据。 / p>

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