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1. 发明申请

WO2016097802A1 MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON LONG LOAD CYCLES IN AN OUT-ORDER PROCESSOR 审中-公开
标题翻译：预防在外部处理者中长期循环的依赖关系的机制
公开(公告)号：WO2016097802A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003215
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/48
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/5011 , G06F2209/507 , Y02D10/22
摘要： An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction requires more than a first number of clock cycles to retrieve the operand. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
摘要翻译：一种装置包括第一和第二保留站。第一保留站（421.L）调度负载微指令，并且在保持总线（444）上指示负载微指令是否是指定的负载微指令，用于从除核心缓存之外的规定资源检索操作数存储器，其中指定的加载指令需要多于第一数量的时钟周期来检索操作数。第二保留站（421.1-421.N）被耦合到保持总线（444），并在其中分派一个或多个依赖于负载微指令执行的一个或多个较小的微指令，以在第一个加载微指令，并且如果在保持总线（444）上指示负载微指令是指定的负载微指令，则第二保留站（421.1-421.N）被配置为停止一个或多个更年轻的微指令，直到加载微指令已经检索到操作数。

2. 发明申请

WO2016097794A1 PREFETCHING WITH LEVEL OF AGGRESSIVENESS BASED ON EFFECTIVENESS BY MEMORY ACCESS TYPE 审中-公开
标题翻译：基于存储器访问类型的有效性预测具有等级
公开(公告)号：WO2016097794A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003175
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HOOKER, Rodney, E. , EDDY, Colin , REED, Douglas, R. , GREER, John, Michael
IPC分类号： G06F9/38
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/30043 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F11/30 , G06F12/0875 , G06F12/1009 , G06F12/127 , G06F2212/1024 , G06F2212/452 , G06F2212/502 , G06F2212/602 , G06F2212/6026 , Y02D10/13
摘要： A processor includes a prefetched 102) that prefetches data in response to memory accesses(134), wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table(106) that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher( 102) prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table(106) and the associated MATs of the memory accesses.
摘要翻译：处理器包括预取存储器访问（134）的预取数据（102），其中每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。处理器还包括表（106），其保存指示预取器相对于多个预定MAT预取数据的有效性的分数。预取器（102）基于保持在表（106）中的分数和存储器访问的相关联的MAT分级，以侵略性水平响应于存储器访问预取数据。

3. 发明申请

WO2016097792A1 APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：根据订单处理程序中写入组合记忆空间访问依据的装载和方法
公开(公告)号：WO2016097792A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003171
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of prescribed resources includes system memory, coupled to the out-of-order processor via a memory bus, where the specified load micro instruction is known to resolve to write combining memory space in the system memory.
摘要翻译：一种包括第一和第二保留站的装置。第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。多个规定资源包括经由存储器总线耦合到无序处理器的系统存储器，其中已知指定的负载微指令解决写入组合系统存储器中的存储器空间。

4. 发明申请

WO2016097793A1 MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON OFF-DIE CONTROL ELEMENT ACCESS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：机构预防负荷补偿依赖于外部控制元件访问超出处理器
公开(公告)号：WO2016097793A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003173
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , GLENN, Henry, G.
IPC分类号： G06F15/163
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3836 , G06F13/36 , Y02D10/14
摘要： An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.
摘要翻译：一种装置包括第一和第二保留站。第一保留站（421.L）调度负载微指令，并且在保持总线（444）上指示负载微指令是否是指定的负载微指令，用于从除核心缓存之外的规定资源检索操作数记忆。第二保留站（421.1-421.N）被耦合到保持总线（444），并在其中分派一个或多个依赖于负载微指令执行的一个或多个较小的微指令，以在第一个加载微指令，并且如果在保持总线（444）上指示负载微指令是指定的负载微指令，则第二保留站（421.1-421.N）被配置为停止一个或多个更年轻的微指令，直到加载微指令已经检索到操作数。多个非核心资源包括经由控制总线耦合到失序处理器的控制元件。

5. 发明申请

WO2016012831A1 SIMULTANEOUS INVALIDATION OF ALL ADDRESS TRANSLATION CACHE ENTRIES ASSOCIATED WITH X86 PROCESS CONTEXT IDENTIFIER 审中-公开
标题翻译：与X86过程相关的所有地址翻译高速缓存的同时失效语境标识符
公开(公告)号：WO2016012831A1
公开(公告)日：2016-01-28
申请号：PCT/IB2014/003110
申请日：2014-11-26
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： EDDY, Colin
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/1027 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F15/7839 , G06F2212/1016 , G06F2212/1044 , G06F2212/683
摘要： A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector, wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID). The TLB also includes an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries. The TLB also includes logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector.
摘要翻译：翻译后备缓冲器（TLB）包括多个条目，其中多个条目的每个条目被配置为保存地址转换和本地有效位向量，其中本地有效位向量的每个位从不同的 x86指令集架构（ISA）进程上下文标识符（PCID）的值。 TLB还包括接收具有与多个条目的本地有效位向量的位对应的位的无效位向量的输入。 TLB还包括同时使对应于无效位向量的设置位的多个条目的每个条目的本地有效位向量的位的同时无效的逻辑。

6. 发明申请

WO2016012830A1 EFFICIENT ADDRESS TRANSLATION CACHING IN PROCESSOR THAT SUPPORTS LARGE NUMBER OF DIFFERENT ADDRESS SPACES 审中-公开
标题翻译：支持大量不同地址空间的处理器中的高效地址转换
公开(公告)号：WO2016012830A1
公开(公告)日：2016-01-28
申请号：PCT/IB2014/003084
申请日：2014-11-26
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： PARKS, Terry , EDDY, Colin , MOHAN, Viswanath , BUNDA, John, D.
IPC分类号： G06F12/10
CPC分类号： G06F12/0891 , G06F12/1027 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F15/7839 , G06F2212/1016 , G06F2212/1044 , G06F2212/683
摘要： A processor includes translation-lookaside buffer (TLB) (206) and a mapping module (204). The TLB (206) includes a plurality of entries (300), wherein each entry of the plurality of entries (300) is configured to hold an address translation (306, 308) and a valid bit vector (302, 304), wherein each bit of the valid bit vector (302, 304) indicates, for a respective address translation context, the address translation (306, 308) is valid if set and invalid if clear. The TLB (206) also includes an invalidation bit vector (302, 304) having bits corresponding to the bits of the valid bit vector (302, 304) of the plurality of entries (300), wherein a set bit of the invalidation bit vector (302, 304) indicates to simultaneously clear the corresponding bit of the valid bit vector (302, 304) of each entry of the plurality of entries (300). The mapping module (204) generates the invalidation bit vector (302, 304).
摘要翻译：处理器包括翻译后备缓冲器（TLB）（206）和映射模块（204）。 TLB（206）包括多个条目（300），其中多个条目（300）的每个条目被配置为保存地址转换（306,308）和有效位向量（302,304），其中每个条目对于相应的地址转换上下文，有效位向量（302,304）的位指示如果设置为无效，则地址转换（306,308）是有效的。 TLB（206）还包括具有对应于多个条目（300）的有效位向量（302,304）的比特的比特的无效比特向量（302,304），其中无效比特向量的设置比特（302,304）指示同时清除多个条目（300）的每个条目的有效位向量（302,304）的对应位。映射模块（204）生成无效位向量（302,304）。

7. 发明申请

WO2016097806A1 FULLY ASSOCIATIVE CACHE MEMORY BUDGETED BY MEMORY ACCESS TYPE 审中-公开
标题翻译：由存储器访问类型预处理的完全相关的高速缓存存储器
公开(公告)号：WO2016097806A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003220
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： LOPEZ, Albert, J. , HOOKER, Rodney, E. , EDDY, Colin , REED, Douglas, R. , GREER, John, Michael
IPC分类号： G06F12/08
CPC分类号： G06F12/0877 , G06F12/0864 , G06F12/0893 , G06F12/122 , G06F12/123 , G06F12/126 , G06F2212/1021 , G06F2212/502 , G06F2212/604
摘要： A fully associative cache memory, comprising: an array of storage elements; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element of the array has an associated MAT. For each MAT, the allocation unit maintains: a counter that counts of a number of valid storage elements associated with the MAT; and a corresponding threshold. The allocation unit allocates into any of the storage elements in response to a memory access that misses in the cache, unless the counter of the MAT of the memory access has reached the corresponding threshold, in which case the allocation unit replaces one of the valid storage elements associated with the MAT of the memory access.
摘要翻译：一种完全关联的高速缓冲存储器，包括：一组存储元件; 分配单元，其响应于在高速缓冲存储器中缺失的存储器访问来分配存储元件。每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。数组的每个有效存储元素都有一个关联的MAT。对于每个MAT，分配单元维护：计数与MAT相关联的多个有效存储元素的计数器; 和相应的阈值。除非存储器访问的MAT的计数器已达到相应的阈值，否则分配单元响应于高速缓存中缺少的存储器访问而分配到任何存储元件中，在这种情况下，分配单元替换有效存储器与MAT相关的元素的内存访问。

8. 发明申请

WO2016097791A1 APPARATUS AND METHOD FOR PROGRAMMABLE LOAD REPLAY PRECLUSION 审中-公开
标题翻译：用于可编程负载重置预处理的装置和方法
公开(公告)号：WO2016097791A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003170
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, Glenn, G.
IPC分类号： G06F9/48
CPC分类号： G06F9/3838 , G06F9/30 , G06F9/30043 , G06F9/3855 , G06F9/5011 , G06F2209/507
摘要： An apparatus includes first reservation and second reservation. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a random access memory, programmed via a Joint Test Action Group interface with the plurality of specified load instructions corresponding to an out-of-order processor which, upon initialization, accesses the random access memory to determine said plurality of specified load instructions.
摘要翻译：一种装置包括第一预约和第二预约。第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。多个非核心资源包括随机存取存储器，其通过联合测试动作组接口编程，其中多个指定的加载指令对应于无序处理器，其在初始化时访问随机存取存储器，以确定所述多个指定的加载指令。

9. 发明申请

WO2016097790A1 APPARATUS AND METHOD TO PRECLUDE NON-CORE CACHE-DEPENDENT LOAD REPLAYS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：预订非处理器中非核心缓存依赖负载复用的装置和方法
公开(公告)号：WO2016097790A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003169
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes an off-core cache memory, configured to store memory operands which may have been cached from a system memory that are not present in one or more on-core cache memories.
摘要翻译：一种包括第一和第二保留站的装置。第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。多个非核心资源包括一个非核心高速缓存存储器，用于存储可能已经从不存在于一个或多个核心高速缓冲存储器中的系统存储器缓存的存储器操作数。

10. 发明申请

WO2016055828A1 CACHE SYSTEM WITH PRIMARY CACHE AND OVERFLOW FIFO CACHE 审中-公开
标题翻译：具有主缓存和超流FIFO缓存的缓存系统
公开(公告)号：WO2016055828A1
公开(公告)日：2016-04-14
申请号：PCT/IB2014/003250
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： EDDY, Colin , HOOKER, Rodney, E.
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/1027 , G06F12/123 , G06F12/128 , G06F2212/1024 , G06F2212/283 , G06F2212/68 , G06F2212/681 , G06F2212/684
摘要： A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is configured as FIFO buffer. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.
摘要翻译：包括使用搜索地址一起搜索的主缓存和溢出高速缓存的高速缓冲存储器系统。溢出缓存作为主缓存的逐出数组。使用搜索地址的位来寻址主缓存，并将溢出缓存配置为FIFO缓冲区。高速缓冲存储器系统可以用于实现微处理器的翻译后备缓冲器。

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