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1. 发明申请

WO2013016168A2 SYSTEMS AND METHODS OF STORING DATA 审中-公开
标题翻译：存储数据的系统和方法
公开(公告)号：WO2013016168A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/047545
申请日：2012-07-20
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
IPC分类号： G06F11/10
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： Systems and methods of storing data are disclosed.
摘要翻译：公开了存储数据的系统和方法。

2. 发明申请

WO2008075351A3 SOFT DECODING OF HARD AND SOFT BITS READ FROM A FLASH MEMORY 审中-公开
公开(公告)号：WO2008075351A3
公开(公告)日：2008-06-26
申请号：PCT/IL2007/001565
申请日：2007-12-19
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , ALROD, Idan , SHARON, Eran , LITSYN, Simon , LASSER, Menahem
发明人： ALROD, Idan , SHARON, Eran , LITSYN, Simon , LASSER, Menahem
IPC分类号： G11C16/26 , G11C11/56 , G06F11/10
摘要： To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimate probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

3. 发明申请

WO2009104063A1 METHOD AND DEVICE FOR ADAPTIVE DECODING USING GLOBAL PARITY BITS 审中-公开
标题翻译：使用全球特征位自适应解码的方法和装置
公开(公告)号：WO2009104063A1
公开(公告)日：2009-08-27
申请号：PCT/IB2008/055477
申请日：2008-12-21
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
IPC分类号： H03M13/29 , G06F11/10 , H03M13/11
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3707 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many- to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。解码终止的子集至少部分地根据所选择的子集被再次解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

4. 发明申请

WO2009156877A1 METHOD AND APPARATUS FOR ERROR CORRECTION ACCORDING TO ERASE COUNTS OF A SOLID-STATE MEMORY 审中-公开
标题翻译：根据固态存储器的擦除次数进行错误校正的方法和装置
公开(公告)号：WO2009156877A1
公开(公告)日：2009-12-30
申请号：PCT/IB2009/051856
申请日：2009-05-06
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , LASSER, Menahem
发明人： ALROD, Idan , SHARON, Eran , LASSER, Menahem
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1068
摘要： Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (H) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.
摘要翻译：本发明的实施例涉及对至少一个固态存储器块维持擦除计数的方法和装置。根据存储器块的相关擦除次数，从固态存储器读取的数据中的错误被校正。在一些实施例中，可以根据从其读取数据的存储器块的相关联的擦除计数来实现以下纠错操作中的一个或多个：（i）选择解码器和/或解码器模式; （H）使用较轻权重解码器（模式）和/或较重权重解码器（模式）和/或更快解码器（模式）和/或较慢解码器（模式）进行纠错的决定; （iii）确定模式转换和/或纠错尝试资源预算; （iv）确定多个软比特; 和（v）选择解码总线宽度大小。

5. 发明申请

WO2009156876A1 FAST, LOW-POWER READING OF DATA IN A FLASH MEMORY 审中-公开
标题翻译：快速，低功耗读取闪存中的数据
公开(公告)号：WO2009156876A1
公开(公告)日：2009-12-30
申请号：PCT/IB2009/051833
申请日：2009-05-05
申请人： SANDISK IL LTD. , ALROD, Idan , LASSER, Menahem
发明人： ALROD, Idan , LASSER, Menahem
IPC分类号： G11C16/26 , G11C16/28 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/28 , G11C2216/14
摘要： A memory includes cells at intersections of word lines and bit lines, word and bit line selection mechanisms and a programming mechanism. The cells on each bit line are connected in series. Cells of a word line are programmed simultaneously. For low-power reading, only some of the bit lines that intersect the word line at the programmed cells are selected and only the cells at those intersections are sensed. Another type of memory includes a physical page of cells, a sensing mechanism and a selection mechanism. Hard bits are sensed from all the cells of the physical page. Only some of those cells are selected for sensing soft bits. Another memory includes a plurality of cells, a sensing mechanism, an export mechanism and a selection mechanism. Hard and soft bits are sensed from all the cells of the plurality. Only some of the soft bits are selected for export.
摘要翻译：存储器包括在字线和位线的交点处的单元，字和位线选择机构以及编程机制。每个位线上的单元串联连接。字线的单元格同时编程。对于低功率读取，仅选择与编程单元处的字线相交的一些位线，并且仅检测那些相交处的单元。另一种类型的存储器包括单元的物理页面，感测机构和选择机构。从物理页面的所有单元格感测硬比特。仅选择这些单元中的一些用于感测软位。另一存储器包括多个单元，感测机构，输出机构和选择机构。从多个单元中的所有单元检测硬和软比特。只有一些软位被选择用于导出。

6. 发明申请

WO2010070427A2 RUGGEDIZED MEMORY DEVICE 审中-公开
标题翻译：强制性存储器件
公开(公告)号：WO2010070427A2
公开(公告)日：2010-06-24
申请号：PCT/IB2009/007784
申请日：2009-12-15
申请人： SANDISK IL LTD. , LASSER, Menahem
发明人： LASSER, Menahem
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1032
摘要： A non-volatile storage device with built-in ruggedized features is disclosed. The device processes a write command to a logical block address by writing the data from the command to a non-volatile memory within the non-volatile storage device and conditionally associating the data received from the command with its corresponding logical block address. Two or more received write commands define a set of commands associated with an atomic transaction. When an end of set command is received, the device unconditionally associates the received data with each write command with its corresponding logical block address. If a power loss interrupts the reception of a set of commands, the non-volatile storage device may recover the last consistent data state before the atomic transaction was started. A write command transaction identifier allows the device to associate the command with a thread of commands that define an atomic transaction in a multithreaded system.
摘要翻译：公开了一种具有内置加固功能的非易失性存储设备。该设备通过将命令中的数据写入非易失性存储设备内的非易失性存储器来处理对逻辑块地址的写入命令，并且将从命令接收的数据与其对应的逻辑块地址有条件地相关联。两个或多个接收的写入命令定义与原子事务相关联的一组命令。当接收到设置命令的结束时，设备无条件地将接收到的数据与每个写命令相关联，并具有相应的逻辑块地址。如果功率损耗中断了一组命令的接收，则非易失性存储设备可以在原子事务开始之前恢复最后一致的数据状态。写命令事务标识符允许设备将命令与在多线程系统中定义原子事务的命令线程相关联。

7. 发明申请

WO2008093327A1 FLASH MEMORY WITH IMPROVED PROGRAMMING PRECISION 审中-公开
标题翻译：具有改进编程精度的闪存
公开(公告)号：WO2008093327A1
公开(公告)日：2008-08-07
申请号：PCT/IL2008/000086
申请日：2008-01-20
申请人： SANDISK IL LTD. , LASSER, Menahem
发明人： LASSER, Menahem
IPC分类号： G11C16/20
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/3427 , G11C2211/5622 , G11C2216/16
摘要： A memory includes a plurality of flash cells and circuitry for programming a first cell to store first data and one or more second cells to store second data. Either the circuitry itself, or a controller of the memory, or a host of the memory by executing driver code, causes the programming of the first cell to be in accordance with the second data, with at least a portion of the programming of the first cell being effected before any of the programming of the second cell(s). Data are stored in cells of a flash memory by assigning a first portion of the data to be stored in a first cell and a second portion of the data to be stored in one or more second cells. The first cell is programmed to store the first portion in accordance with the second portion. The second cell(s) is/are programmed to store the second portion. At least a portion of the programming of the first cell is effected before any of the programming of the second cell(s).
摘要翻译：存储器包括多个闪存单元和用于编程第一单元以存储第一数据的电路和用于存储第二数据的一个或多个第二单元。通过执行驱动程序代码，电路本身或存储器的控制器或存储器的主机使得第一单元的编程与第二数据一致，至少部分编程的第一个在第二小区的任何编程之前实现小区。通过将待存储的数据的第一部分分配给要存储在一个或多个第二单元中的第一单元和数据的第二部分，将数据存储在闪存的单元中。第一单元被编程为根据第二部分存储第一部分。第二单元被编程为存储第二部分。第一小区的编程的至少一部分在任何第二小区的编程之前被实现。

8. 发明申请

WO2007129293A3 CORRUPTION-RESISTANT DATA PORTING WITH MULTIPLE ERROR CORRECTION SCHEMES 审中-公开
公开(公告)号：WO2007129293A3
公开(公告)日：2007-11-15
申请号：PCT/IL2006/001249
申请日：2006-10-30
申请人： MSYSTEMS LTD. , LASSER, Menahem
发明人： LASSER, Menahem
IPC分类号： H03M13/00
摘要： To export (e.g. store or transmit)(50) input data, only the input data are encoded (34) separately according to first and second encoding schemes (30) tp rovide first and second encoded data. The first encoded data and the second encoded data data are exported (48). Upon importimg (e.g., retriving or receiving) representations of the exported data, a first decoding scheme is applied to the representation of the first encoded data to recover the input data (42). If that application fails, then a second decoding scheme is applied to the representation of the second encoded data to recover the input data.

9. 发明申请

WO2010023529A1 MULTIPLE PERFORMANCE MODE MEMORY SYSTEM 审中-公开
标题翻译：多种性能模式存储系统
公开(公告)号：WO2010023529A1
公开(公告)日：2010-03-04
申请号：PCT/IB2009/006615
申请日：2009-08-21
申请人： SANDISK IL LTD , LASSER, Menahem
发明人： LASSER, Menahem
IPC分类号： G11C16/20 , G06F12/02
CPC分类号： G11C16/20 , G06F13/385
摘要： A method and system for controlling a write performance level of a memory is disclosed. The method includes receiving an input at the memory, and configuring the memory to an operation mode providing a write performance level and a storage capacity. The input may specify a storage capacity, a working area capacity, a write performance level, and/or a ratio of the storage capacity to the working area capacity. A desired write performance level may be set by receiving a software command or hardware setting. The storage capacity may be varied depending on whether the memory device has been formatted. As the storage capacity decreases, working area capacity of the memory device increases and write performance increases. Conversely, as the storage capacity increases, working area capacity decreases and write performance decreases.
摘要翻译：公开了一种用于控制存储器的写入性能水平的方法和系统。该方法包括在存储器处接收输入，并将存储器配置为提供写入性能水平和存储容量的操作模式。输入可以指定存储容量，工作区容量，写入性能级别和/或存储容量与工作区容量的比率。可以通过接收软件命令或硬件设置来设置期望的写入性能级别。存储容量可以根据存储器件是否被格式化而变化。随着存储容量的降低，存储器件的工作区容量增加，写入性能提高。相反，随着存储容量的增加，工作区容量下降，写性能下降。

10. 发明申请

WO2009153781A1 REVERSE ORDER PAGE WRITING IN FLASH MEMORIES 审中-公开
标题翻译：闪存中的反序列表
公开(公告)号：WO2009153781A1
公开(公告)日：2009-12-23
申请号：PCT/IL2009/000592
申请日：2009-06-15
申请人： SANDISK IL LTD. , LASSER, Menahem
发明人： LASSER, Menahem
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to anyone of the word lines has a higher logical page address than any page that is written to a subsequently written word line, regardless of the sequence in which the pages are received for writing. Alternatively, the pages are written to the word lines so that for every pair of written word lines, the word line of the pair that is earlier in the writing order has written thereto a page having a higher logical page address than at least one page written to the other word line of the pair.
摘要翻译：要在字线写入顺序中连续写入字线的存储块中存储由逻辑页面地址排序的多个数据页，将页写入字线，以便写入任何一个页面的每个页面的字线具有比写入随后写入的字线的任何页面更高的逻辑页面地址，而不管页面被接收以用于写入的顺序。或者，页面被写入字线，使得对于每对写入的字线，在写入顺序中较早的对中的字线已写入具有比至少一个页面写入的更高逻辑页地址的页面到对的另一个字线。

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