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    • 5. 发明申请
    • ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS
    • 具有减少内存和电源要求的错误修正解码
    • WO2013018080A1
    • 2013-02-07
    • PCT/IL2011/000617
    • 2011-07-31
    • SANDISK TECHNOLOGIES, INC., A TEXAS CORPORATIONSHARON, EranALROD, IdanFAINZILBER, OmerLITSYN, Simon
    • SHARON, EranALROD, IdanFAINZILBER, OmerLITSYN, Simon
    • H03M13/00
    • H03M13/1105H03M13/1117H03M13/3715H03M13/6502
    • An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
    • 提供了一种示例性方法,其包括接收包括多个比特的码字的表示,并且将比特与表示比特的相应多个一比特硬比特值和表示多个比特的度量的多比特软比特值相关联 各个硬比特值的可靠性。 该方法包括用于多个迭代中的每一个,作为该子集的比特的当前硬比特值的函数来更新比特的相应子集的一个或多个比特的硬比特/软比特值,以及当前 相应位的硬比特和软比特值。 对于两次迭代,其中对于两次迭代的子集的每个位的当前硬比特和软比特值是相同的,则在两次迭代之一期间为子集的任何比特更新的硬比特/软比特值 与在两次迭代中的另一个中相应位计算的相同。
    • 6. 发明申请
    • METHOD AND APPARATUS FOR ERROR CORRECTION ACCORDING TO ERASE COUNTS OF A SOLID-STATE MEMORY
    • 根据固态存储器的擦除次数进行错误校正的方法和装置
    • WO2009156877A1
    • 2009-12-30
    • PCT/IB2009/051856
    • 2009-05-06
    • SANDISK IL LTD.ALROD, IdanSHARON, EranLASSER, Menahem
    • ALROD, IdanSHARON, EranLASSER, Menahem
    • G06F11/10G06F11/00
    • G06F11/1068
    • Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (H) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.
    • 本发明的实施例涉及对至少一个固态存储器块维持擦除计数的方法和装置。 根据存储器块的相关擦除次数,从固态存储器读取的数据中的错误被校正。 在一些实施例中,可以根据从其读取数据的存储器块的相关联的擦除计数来实现以下纠错操作中的一个或多个:(i)选择解码器和/或解码器模式; (H)使用较轻权重解码器(模式)和/或较重权重解码器(模式)和/或更快解码器(模式)和/或较慢解码器(模式)进行纠错的决定; (iii)确定模式转换和/或纠错尝试资源预算; (iv)确定多个软比特; 和(v)选择解码总线宽度大小。