专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013147936A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMNMING 审中-公开
标题翻译：在编程期间选定的字线相关选择门限扩展区域电压
公开(公告)号：WO2013147936A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066610
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
发明人： LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

2. 发明申请

WO2013147937A1 SELECTED WORD LINE DEPENDENT SELECT GAME VOLTAGE DURING PROGRAM 审中-公开
标题翻译：在程序期间选择的字线相关选择游戏电压
公开(公告)号：WO2013147937A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066611
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , LAI, Chun-hung , DUTTA, Deepanshu , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： LAI, Chun-hung , DUTTA, Deepanshu , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

3. 发明申请

WO2014088803A1 NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 审中-公开
标题翻译：非易失性存储NAND STRING在编程期间选择门电压降低
公开(公告)号：WO2014088803A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/070841
申请日：2013-11-19
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
摘要： Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
摘要翻译：本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。因此，防止或减少程序干扰。可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。

4. 发明申请

WO2006036453A3 NON-VOLATILE NAND MEMORY WITH ASYMMETRICAL DOPING PROFILE 审中-公开
公开(公告)号：WO2006036453A3
公开(公告)日：2006-04-06
申请号：PCT/US2005/031279
申请日：2005-08-26
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , SATO, Shinji
发明人： HEMINK, Gerrit, Jan , SATO, Shinji
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788 , G11C16/04
摘要： Stacked gate structures (408A,480B,480C) for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantation’s are performed at a 5-second implantation angle to areas between the stacked gate structures. The drain implantations (498) create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations (496) create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures. A B-halo (494) can be formed as well.

5. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

6. 发明申请

WO2011103013A1 NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION BASED ON NEIGHBOR STATE INFORMATION 审中-公开
标题翻译：基于邻国状态信息的温度补偿非挥发性储存
公开(公告)号：WO2011103013A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/024287
申请日：2011-02-10
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , SATO, Shinji
发明人： HEMINK, Gerrit, Jan , SATO, Shinji
IPC分类号： G11C11/56
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642
摘要： Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
摘要翻译：数据被编程到一组目标存储器单元中并从其读取。读取数据时，提供温度补偿。温度补偿基于温度信息和一个或多个相邻存储单元的状态。在一个实施例中，当从目标存储器单元的集合读取数据时，系统感测当前温度并确定当前温度与数据编程时的温度之间的温度差。如果温度差大于阈值，则读取数据的过程包括基于温度信息和邻近状态信息提供温度补偿。在一个替代方案中，提供温度补偿的决定可以由温差以外的条件触发。

7. 发明申请

WO2013096564A1 NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE 审中-公开
标题翻译：具有三层浮动门的非挥发性储存系统
公开(公告)号：WO2013096564A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/070833
申请日：2012-12-20
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGAHSITANI, Masaaki , ZHAO, Dengtao , LEE, Sanghyun
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGAHSITANI, Masaaki , ZHAO, Dengtao , LEE, Sanghyun
IPC分类号： H01L21/28 , H01L29/788 , G11C16/04 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： G11C16/10 , G11C16/0483 , H01L21/28273 , H01L27/11524 , H01L29/66825 , H01L29/788 , H01L29/7887
摘要： A non-volatile storage system includes memory cells with floating gates (104FG) that comprises three layers separated by two dielectric layers, an upper dielectric layer (UDL) and a lower dielectric layer (LDL). The dielectric layers may be oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate, near the interface between floating gate and tunnel dielectric (TD), while the upper dielectric layer is close to top of the floating gate, near the interface between floating gate and inter-gate dielectric (IGD).
摘要翻译：非易失性存储系统包括具有浮动栅极（104FG）的存储单元，其包括由两个电介质层分离的三层，上介电层（UDL）和下介电层（LDL）。电介质层可以是氧化物层，氮化物层，氧化物和氮化物的组合，或一些其它合适的电介质材料。下电介质层靠近浮动栅极的底部，靠近浮动栅极和隧道电介质（TD）之间的界面，而上部介电层靠近浮动栅极的顶部，靠近浮动栅极和沟道间介质之间的界面，栅极电介质（IGD）。

8. 发明申请

WO2013169509A1 CHANNEL BOOSTING USING SECONDARY NEIGHBOR CHANNEL COUPLING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中使用二次邻域信道耦合的信道增强
公开(公告)号：WO2013169509A1
公开(公告)日：2013-11-14
申请号：PCT/US2013/038596
申请日：2013-04-29
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , YANO, Fumiko
发明人： DUTTA, Deepanshu , SATO, Shinji , YANO, Fumiko
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements. The coupling is helpful to boost channel regions of the unselected storage elements to a higher channel potential to prevent program disturb. Each selected storage element has a different relative position within its set. For example, during a first programming pulse, first, second and third storage elements are selected in first, second and third sets, respectively. During a second programming pulse, second, third and first storage elements are selected in the first, second and third sets, respectively. During a third programming pulse, third, first and second storage elements are selected in the first, second and third sets, respectively.
摘要翻译：在非易失性存储系统中，程序验证迭代的编程部分具有多个编程脉冲，并且根据模式选择沿字线的存储元件进行编程。未选择的存储元件被分组以从主要和次要邻居存储元件的通道到通道的电容耦合受益。耦合有助于将未选择的存储元件的通道区域升高到更高的通道电位，以防止程序干扰。每个选定的存储元件在其集合内具有不同的相对位置。例如，在第一编程脉冲期间，分别在第一，第二和第三组中选择第一，第二和第三存储元件。在第二编程脉冲期间，分别在第一，第二和第三组中选择第二，第三和第一存储元件。在第三编程脉冲期间，分别在第一，第二和第三组中选择第三，第一和第二存储元件。

9. 发明申请

WO2012091162A1 LIQUID IMMERSION MEMBER AND CLEANING METHOD 审中-公开
标题翻译：液体浸泡会员和清洁方法
公开(公告)号：WO2012091162A1
公开(公告)日：2012-07-05
申请号：PCT/JP2011/080580
申请日：2011-12-27
申请人： NIKON CORPORATION , SATO, Shinji
发明人： SATO, Shinji
IPC分类号： G03F7/20
CPC分类号： G03F7/708 , G03F7/70216 , G03F7/70341 , G03F7/70925
摘要： A liquid immersion member (3) comprises: a first liquid immersion member (31), which is disposed at least partly around an optical path (K), that forms a first immersion space (LSI) of a first liquid (LQ) at an emergent surface side (7) of an optical member (8) such that the optical path of exposure light (EL) between the optical member and a substrate (P) is filled with the first liquid; and a second liquid immersion member (32), which is disposed at the outer side of the first liquid immersion member, that forms a second immersion space (LS2) of a second liquid (LQ) partly around the first immersion space and adjacent to a first guide space (A2). A cleaning method comprises: supplying a cleaning liquid (LC) such that it contacts at least part of the first liquid immersion member; and recovering at least some of the cleaning liquid from the first liquid immersion member via an opening (S2) belonging to the second liquid immersion member.
摘要翻译：液浸部件（3）包括：至少部分地围绕光路（K）设置的第一液浸部件（31），其形成第一液体（LQ）的第一浸没空间（LSI）光学构件（8）的出射表面侧（7），使得光学构件和基底（P）之间的曝光光（EL）的光路被第一液体填充; 以及第二液浸部件（32），其设置在所述第一液浸部件的外侧，部分地围绕所述第一浸没空间形成第二液体（LQ）的第二浸没空间（LS2），并且邻近所述第二浸液部件第一引导空间（A2）。一种清洁方法，包括：提供清洗液体，使其与第一液浸部件的至少一部分接触; 以及经由属于所述第二液浸部件的开口（S2）从所述第一液浸部件回收至少一部分所述清洗液。

10. 发明申请

WO2010114682A1 FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION 审中-公开
标题翻译：制作和操作具有多层细胞区域和单层细胞区域的记忆阵列
公开(公告)号：WO2010114682A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/026674
申请日：2010-03-09
申请人： SANDISK CORPORATION , ITO, Fumitoshi , SATO, Shinji
发明人： ITO, Fumitoshi , SATO, Shinji
IPC分类号： G11C11/56
CPC分类号： G11C11/5621 , G11C2211/5641
摘要： Techniques are disclosed herein for applying different process steps to single- level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
摘要翻译：本文公开了将技术应用于存储器阵列中的单级单元（SLC）块而不是多级单元（MLC）块的不同处理步骤，使得SLC块将具有高耐久性并且MLC块将具有高可靠性。在一些方面，在MLC块中使用与SLC块不同的掺杂。在某些方面，在MLC块中使用与SLC块不同的隔离。公开了根据块被编程/擦除多少次来应用不同读取参数的技术。因此，使用与循环次数少的块不同的参数来读取已循环多次的块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式