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1. 发明申请

WO2014088803A1 NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 审中-公开
标题翻译：非易失性存储NAND STRING在编程期间选择门电压降低
公开(公告)号：WO2014088803A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/070841
申请日：2013-11-19
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
摘要： Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
摘要翻译：本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。因此，防止或减少程序干扰。可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。

2. 发明申请

WO2013169509A1 CHANNEL BOOSTING USING SECONDARY NEIGHBOR CHANNEL COUPLING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中使用二次邻域信道耦合的信道增强
公开(公告)号：WO2013169509A1
公开(公告)日：2013-11-14
申请号：PCT/US2013/038596
申请日：2013-04-29
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , YANO, Fumiko
发明人： DUTTA, Deepanshu , SATO, Shinji , YANO, Fumiko
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements. The coupling is helpful to boost channel regions of the unselected storage elements to a higher channel potential to prevent program disturb. Each selected storage element has a different relative position within its set. For example, during a first programming pulse, first, second and third storage elements are selected in first, second and third sets, respectively. During a second programming pulse, second, third and first storage elements are selected in the first, second and third sets, respectively. During a third programming pulse, third, first and second storage elements are selected in the first, second and third sets, respectively.
摘要翻译：在非易失性存储系统中，程序验证迭代的编程部分具有多个编程脉冲，并且根据模式选择沿字线的存储元件进行编程。未选择的存储元件被分组以从主要和次要邻居存储元件的通道到通道的电容耦合受益。耦合有助于将未选择的存储元件的通道区域升高到更高的通道电位，以防止程序干扰。每个选定的存储元件在其集合内具有不同的相对位置。例如，在第一编程脉冲期间，分别在第一，第二和第三组中选择第一，第二和第三存储元件。在第二编程脉冲期间，分别在第一，第二和第三组中选择第二，第三和第一存储元件。在第三编程脉冲期间，分别在第一，第二和第三组中选择第三，第一和第二存储元件。

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