专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2014004095A1 SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION 审中-公开
标题翻译：在擦除操作期间减少字线选择晶体管的压力的系统
公开(公告)号：WO2014004095A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/045585
申请日：2013-06-13
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C11/56
CPC分类号： G11C16/16 , G11C8/08 , G11C11/5635 , G11C16/08 , G11C16/14
摘要： A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
摘要翻译：一种用于擦除非易失性存储系统的系统，其降低了在字线和全局控制线之间接合的字线选择晶体管两端的电压。在字线选择晶体管两端使用较低的电压允许使字线选择晶体管更小。使用更小的组件允许非易失性存储系统包括更多的存储器单元，从而提供存储更多数据的能力。

2. 发明申请

WO2010080674A1 SENSING CIRCUIT AND METHOD WITH REDUCED SUSCEPTIBILITY TO SPATIAL AND TEMPERATURE VARIATIONS 审中-公开
标题翻译：传感电路和降低对空间和温度变化的可靠性的方法
公开(公告)号：WO2010080674A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/069703
申请日：2009-12-29
申请人： SANDISK CORPORATION , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26
摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit (106) that includes a sensing device (104) and a sense transistor (287) coupled to the sensing device. A first switch (288) that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches (282, 293, 291, 289) that are coupled to the sensing device and to a target element (10). The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.
摘要翻译：公开了一种读出放大器。一个实施例是感测电路（106），其包括耦合到感测装置的感测装置（104）和感测晶体管（287）。耦合到感测晶体管和感测装置的第一开关（288）使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。耦合到感测装置和目标元件（10）的一个或多个第二开关（282,293,291,289）。第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通感测晶体管来确定。

3. 发明申请

WO2013188019A1 IMPROVED BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的擦除操作期间改进的位线BL分离方案
公开(公告)号：WO2013188019A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/039778
申请日：2013-05-06
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan, Vamsi , KIM, Kwang-Ho , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , KIM, Kwang-Ho , HIGASHITANI, Masaaki
IPC分类号： G11C7/12 , G11C16/14 , G11C16/06 , G11C16/26 , G11C16/24
CPC分类号： G11C16/24 , G11C7/12 , G11C16/06 , G11C16/14 , G11C16/26
摘要： A system for erasing non-volatile storage system that reduces the voltage across the transistor (600) that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
摘要翻译：一种用于擦除非易失性存储系统的系统，其降低了在感测放大器和位线之间接口的晶体管（600）两端的电压，使得可以使晶体管更小。此外，使用较低的电压允许各种组件彼此更靠近地定位。组件之间使用较小的组件和较小空间允许非易失性存储系统包含更多的存储单元，从而提供存储更多数据的能力。

4. 发明申请

WO2013062936A1 BACK-BIASING WORD LINE SWITCH TRANSISTORS 审中-公开
标题翻译：反向偏移字线开关晶体管
公开(公告)号：WO2013062936A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/061421
申请日：2012-10-23
申请人： SANDISK TECHNOLOGIES, INC. , TOYAMA, Fumiaki , HIGASHITANI, Masaaki
发明人： TOYAMA, Fumiaki , HIGASHITANI, Masaaki
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/08
摘要： Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line switch transistors may be biased separately from the well of the non-volatile storage devices. While programming the non-volatile storage devices, a negative voltage may be applied to the well of the word line switch transistors. This may reduce the voltage that needs to be applied to the gate of a WL switch transistor to pass the program voltage to the selected word line. Therefore, charge pumps can be made smaller, since the maximum voltage they need to generate is smaller. A word line switch transistor may be back-biased during a read operation to pass a negative read compare voltage to a selected word line.
摘要翻译：公开了背偏置字线开关晶体管。一个实施例包括位于衬底中的阱中的字线开关晶体管。具有非易失性存储装置的存储器阵列可以在衬底中的单独的阱中。字线开关晶体管的阱可以与非易失性存储器件的阱分开偏置。在对非易失性存储设备进行编程时，可以向字线开关晶体管的阱施加负电压。这可以降低需要施加到WL开关晶体管的栅极的电压，以将编程电压传递到所选择的字线。因此，可以使电荷泵更小，因为它们需要产生的最大电压较小。在读取操作期间，字线开关晶体管可以被反向偏置，以将负的读取比较电压传递到所选择的字线。

5. 发明申请

WO2013158556A1 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 审中-公开
标题翻译：具有选择性抑制通过位置的3D非易失性存储器的软擦除操作
公开(公告)号：WO2013158556A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036615
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/16 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

6. 发明申请

WO2014066263A1 DYNAMIC BIT LINE BIAS FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于编程非易失性存储器的动态位线偏移
公开(公告)号：WO2014066263A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/065969
申请日：2013-10-21
申请人： SANDISK TECHNOLOGIES,INC. , DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C11/56 , G11C16/12 , G11C7/12 , G11C16/24
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的编程脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

7. 发明申请

WO2013180893A1 THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：堆叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：WO2013180893A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/039505
申请日：2013-05-03
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C29/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

8. 发明申请

WO2013158557A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 审中-公开
标题翻译：具有可控门控感应漏水电流的3D非易失性存储器的擦除操作
公开(公告)号：WO2013158557A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036616
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以受益于更高的栅极引起的漏极泄漏（GIDL）电流以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

9. 发明申请

WO2014071175A1 INTEGRATION OF SINGLE-LEVEL AND MULTI-LEVEL FLASH CELLS HAVING DIFFERENT TUNNEL OXIDE THICKNESSES 审中-公开
标题翻译：具有不同隧道氧化物厚度的单层和多层闪电池的整合
公开(公告)号：WO2014071175A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/068036
申请日：2013-11-01
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , DUNGA, Mohan , YUAN, Jiahui
发明人： HIGASHITANI, Masaaki , DUNGA, Mohan , YUAN, Jiahui
IPC分类号： H01L21/28 , G11C11/56 , H01L27/115
CPC分类号： G11C11/5628 , G11C2211/5641 , H01L21/28273 , H01L27/11521 , H01L27/11524
摘要： Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide (712b) may be used for memory cells in SLC blocks (202b) than for memory cells in MLC blocks (202a). A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide (712a) in MLC blocks may improve data retention. A thinner IPD (708b) may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD (708a) in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks.
摘要翻译：公开了具有与MLC块不同特性的SLC块的技术，使得SLC块将具有高耐久性，并且MLC块将具有高可靠性。较薄的隧道氧化物（712b）可用于SLC块（202b）中的存储器单元而不是MLC块（202a）中的存储单元。 SLC块中较薄的隧道氧化物可能允许使用较低的编程电压，这可以提高耐久性。 MLC块中较厚的隧道氧化物（712a）可以改善数据保留。可以将较薄的IPD（708b）用于SLC块中的存储单元，而不是MLC块中的存储单元。更薄的IPD可以提供更高的耦合比，这可以允许较低的编程电压。 SLC块中较低的编程电压可以提高耐久性。 MLC块中较厚的IPD（708a）可以防止或减少读取干扰。 SLC块可以具有与MLC块不同数量的数据字线。

10. 发明申请

WO2014088803A1 NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 审中-公开
标题翻译：非易失性存储NAND STRING在编程期间选择门电压降低
公开(公告)号：WO2014088803A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/070841
申请日：2013-11-19
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
摘要： Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
摘要翻译：本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。因此，防止或减少程序干扰。可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式