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1. 发明申请

WO2013188019A1 IMPROVED BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的擦除操作期间改进的位线BL分离方案
公开(公告)号：WO2013188019A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/039778
申请日：2013-05-06
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan, Vamsi , KIM, Kwang-Ho , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , KIM, Kwang-Ho , HIGASHITANI, Masaaki
IPC分类号： G11C7/12 , G11C16/14 , G11C16/06 , G11C16/26 , G11C16/24
CPC分类号： G11C16/24 , G11C7/12 , G11C16/06 , G11C16/14 , G11C16/26
摘要： A system for erasing non-volatile storage system that reduces the voltage across the transistor (600) that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
摘要翻译：一种用于擦除非易失性存储系统的系统，其降低了在感测放大器和位线之间接口的晶体管（600）两端的电压，使得可以使晶体管更小。此外，使用较低的电压允许各种组件彼此更靠近地定位。组件之间使用较小的组件和较小空间允许非易失性存储系统包含更多的存储单元，从而提供存储更多数据的能力。

2. 发明申请

WO2014004095A1 SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION 审中-公开
标题翻译：在擦除操作期间减少字线选择晶体管的压力的系统
公开(公告)号：WO2014004095A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/045585
申请日：2013-06-13
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C11/56
CPC分类号： G11C16/16 , G11C8/08 , G11C11/5635 , G11C16/08 , G11C16/14
摘要： A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
摘要翻译：一种用于擦除非易失性存储系统的系统，其降低了在字线和全局控制线之间接合的字线选择晶体管两端的电压。在字线选择晶体管两端使用较低的电压允许使字线选择晶体管更小。使用更小的组件允许非易失性存储系统包括更多的存储器单元，从而提供存储更多数据的能力。

3. 发明申请

WO2010080674A1 SENSING CIRCUIT AND METHOD WITH REDUCED SUSCEPTIBILITY TO SPATIAL AND TEMPERATURE VARIATIONS 审中-公开
标题翻译：传感电路和降低对空间和温度变化的可靠性的方法
公开(公告)号：WO2010080674A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/069703
申请日：2009-12-29
申请人： SANDISK CORPORATION , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26
摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit (106) that includes a sensing device (104) and a sense transistor (287) coupled to the sensing device. A first switch (288) that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches (282, 293, 291, 289) that are coupled to the sensing device and to a target element (10). The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.
摘要翻译：公开了一种读出放大器。一个实施例是感测电路（106），其包括耦合到感测装置的感测装置（104）和感测晶体管（287）。耦合到感测晶体管和感测装置的第一开关（288）使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。耦合到感测装置和目标元件（10）的一个或多个第二开关（282,293,291,289）。第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通感测晶体管来确定。

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