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1. 发明申请

WO2008124503A1 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 审中-公开
标题翻译：包括缓冲器器件和集成电路存储器件的存储器系统拓扑
公开(公告)号：WO2008124503A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/059268
申请日：2008-04-03
申请人： RAMBUS INCORPORATED , TSERN, Ely , SHAEFFER, Ian , HAMPEL, Craig
发明人： TSERN, Ely , SHAEFFER, Ian , HAMPEL, Craig
IPC分类号： G11C5/06 , G11C7/10 , G11C5/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点对点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

2. 发明申请

WO2005116838A1 CONFIGURABLE WIDTH BUFFERED MODULE HAVING A BYPASS CIRCUIT 审中-公开
标题翻译：具有旁路电路的可配置宽度缓冲模块
公开(公告)号：WO2005116838A1
公开(公告)日：2005-12-08
申请号：PCT/US2005/017066
申请日：2005-05-16
申请人： RAMBUS INCORPORATED , PEREGO, Richard , WARE, Fred , TSERN, Ely , HAMPEL, Craig
发明人： PEREGO, Richard , WARE, Fred , TSERN, Ely , HAMPEL, Craig
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G06F13/1684 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1806 , H05K1/181
摘要： A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel. In an alternate embodiment of the present invention, two bypass circuits are coupled to a pair of entry and exit pins. In an embodiment of the present invention, a memory system may include at least four interfaces, or sockets, for respective memory modules having configurable width buffer devices with bypass circuits that enable additional upgrade options while reducing memory system access delays.
摘要翻译：存储器系统架构/互连拓扑包括具有可配置宽度缓冲器件的可配置宽度缓冲存储器模块，其具有至少一个旁路电路。诸如可配置的宽度缓冲器装置之类的缓冲装置被定位在位于诸如DIMM之类的存储器模块的衬底表面上的至少一个集成电路存储器件之间或之间。可配置宽度缓冲器件耦合到存储器模块上的至少一个存储器件（通过内部通道），入口引脚和引脚。可配置宽度缓冲器件包括耦合到入口引脚和用于访问存储器件的内部通道的多路复用器/解复用器电路。旁路电路耦合到入口引脚和出口引脚，以便允许信息通过存储器模块通过外部通道传送到存储器系统中的另一个耦合的存储器模块。在本发明的替代实施例中，两个旁路电路耦合到一对入口和出口销。在本发明的一个实施例中，存储器系统可以包括至少四个接口或插座，用于具有可配置的宽度缓冲器设备的相应存储器模块，该旁路电路能够实现额外的升级选项，同时减少存储器系统访问延迟。

3. 发明申请

WO2007136655A3 SYSTEM TO DETECT AND IDENTIFY ERRORS IN CONTROL INFORMATION, READ DATA AND/OR WRITE DATA 审中-公开
公开(公告)号：WO2007136655A3
公开(公告)日：2007-11-29
申请号：PCT/US2007/011733
申请日：2007-05-16
申请人： RAMBUS INCORPORATED , SHAEFFER, Ian , HAMPEL, Craig
发明人： SHAEFFER, Ian , HAMPEL, Craig
IPC分类号： G06F11/10
摘要： An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.

4. 发明申请

WO2011106056A1 METHODS AND CIRCUITS FOR DYNAMICALLY SCALING DRAM POWER AND PERFORMANCE 审中-公开
标题翻译：用于动态调整DRAM功率和性能的方法和电路
公开(公告)号：WO2011106056A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058555
申请日：2010-12-01
申请人： RAMBUS INC. , TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
发明人： TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
IPC分类号： G11C11/4074 , G11C11/4063 , G11C11/408 , G06F13/14
CPC分类号： G06F3/0625 , G06F1/266 , G06F3/0634 , G06F3/0673 , G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
摘要翻译：内存系统支持高性能和低功耗模式。存储器系统包括存储器核和核心接口。存储器内核采用在两种模式下保持相同的核心电源电压。核心接口的电源电压和信号速率可以缩小以节省功耗。存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

5. 发明申请

WO2008121559A1 SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES OF INTEGRATED CIRCUIT MEMORY DEVICES 审中-公开
标题翻译：包括具有不同类型的集成电路存储器件的分层存储器模块的系统
公开(公告)号：WO2008121559A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/057471
申请日：2008-03-19
申请人： RAMBUS INCORPORATED , HAMPEL, Craig , HOROWITZ, Mark
发明人： HAMPEL, Craig , HOROWITZ, Mark
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G11C29/1201 , G06F3/0611 , G06F3/0614 , G06F3/0647 , G06F3/0688 , G06F12/08 , G06F12/0804 , G06F12/0851 , G06F12/0897 , G06F13/1684 , G06F2212/2022 , G06F2212/205 , G06F2212/3042 , G06F2212/608 , G11C5/04 , G11C7/10 , G11C7/1003 , G11C29/12 , G11C29/12015 , G11C29/32 , G11C29/76 , G11C2029/3202 , Y02D10/13 , Y02D10/14
摘要： A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.
摘要翻译：公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。模块中包含第一个集成电路缓冲器。该系统具有定义第二存储器层级的第二组非易失性存储器件。第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。第二模块包括第二集成电路缓冲装置。该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

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