专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012027250A1 MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING 审中-公开
标题翻译：具有自适应切换的存储方法和系统
公开(公告)号：WO2012027250A1
公开(公告)日：2012-03-01
申请号：PCT/US2011/048571
申请日：2011-08-22
申请人： RAMBUS INC. , VOGELSANG, Thomas , HAUKNESS, Brent
发明人： VOGELSANG, Thomas , HAUKNESS, Brent
IPC分类号： G11C7/10 , G11C5/14 , G11C7/06 , G11C7/22
CPC分类号： G11C5/147 , G11C7/00 , G11C7/08 , G11C7/12 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C11/4094
摘要： A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.
摘要翻译：存储器系统包括提供对存储器存储元件的访问的字线和互补位线对。与字线和位线相关的电容和电阻负载在电压电平之间相对较慢地驱动，以降低峰值电流，从而降低功耗。通过以基本不同的速率充电补充位线来进一步降低功耗。

2. 发明申请

WO2011106262A4 HIERARCHICAL MEMORY ARCHITECTURE 审中-公开
标题翻译：分层存储器体系结构
公开(公告)号：WO2011106262A4
公开(公告)日：2011-09-01
申请号：PCT/US2011/025487
申请日：2011-02-18
申请人： RAMBUS INC. , VOGELSANG, Thomas , HAUKNESS, Brent
发明人： VOGELSANG, Thomas , HAUKNESS, Brent
IPC分类号： G11C7/12 , G11C8/08 , G11C29/00
摘要： A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column- select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.
摘要翻译：分层存储器体系结构包括存储器子阵列阵列，每个存储器阵列阵列包括存储器单元阵列。每个子阵列由本地字线，本地列选择线和位线支持。使用主字线控制局部字线，所述主字线在平行于第一轴的方向上延伸经过多个子阵列，而局部列选择线使用在子阵列之间在垂直于第一轴。在呈现在本地字线和列选择线上的信号的方向上，每个子阵列中的位线的子集连接到主数据线，主数据线在与第二轴平行的多个子阵列上延伸。一些实施例包括基于行地址的解码选择的冗余数据资源。

3. 发明申请

WO2013015893A1 MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION 审中-公开
标题翻译：记忆与诽谤的活动
公开(公告)号：WO2013015893A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/041758
申请日：2012-06-08
申请人： RAMBUS INC. , HARRIS, James, Edward , VOGELSANG, Thomas , WARE, Frederick, A. , SHAEFFER, Ian, P.
发明人： HARRIS, James, Edward , VOGELSANG, Thomas , WARE, Frederick, A. , SHAEFFER, Ian, P.
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
摘要翻译：存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

4. 发明申请

WO2011139496A2 TECHNIQUES FOR INTERCONNECTING STACKED DIES USING CONNECTION SITES 审中-公开
标题翻译：使用连接站点互连堆叠式工具的技术
公开(公告)号：WO2011139496A2
公开(公告)日：2011-11-10
申请号：PCT/US2011/032197
申请日：2011-04-13
申请人： RAMBUS INC. , WARE, Frederick A. , TSERN, Ely , VOGELSANG, Thomas
发明人： WARE, Frederick A. , TSERN, Ely , VOGELSANG, Thomas
IPC分类号： H01L23/52 , H01L23/538
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外部的核心电路。核心电路耦合到至少一个连接位置。

5. 发明申请

WO2012082480A3 MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING 审中-公开
公开(公告)号：WO2012082480A3
公开(公告)日：2012-06-21
申请号：PCT/US2011/063657
申请日：2011-12-07
申请人： RAMBUS INC. , VOGELSANG, Thomas
发明人： VOGELSANG, Thomas
IPC分类号： G11C5/06 , G11C5/02 , G11C11/40
摘要： A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines.

6. 发明申请

WO2011106056A1 METHODS AND CIRCUITS FOR DYNAMICALLY SCALING DRAM POWER AND PERFORMANCE 审中-公开
标题翻译：用于动态调整DRAM功率和性能的方法和电路
公开(公告)号：WO2011106056A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058555
申请日：2010-12-01
申请人： RAMBUS INC. , TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
发明人： TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
IPC分类号： G11C11/4074 , G11C11/4063 , G11C11/408 , G06F13/14
CPC分类号： G06F3/0625 , G06F1/266 , G06F3/0634 , G06F3/0673 , G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
摘要翻译：内存系统支持高性能和低功耗模式。存储器系统包括存储器核和核心接口。存储器内核采用在两种模式下保持相同的核心电源电压。核心接口的电源电压和信号速率可以缩小以节省功耗。存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

7. 发明申请

WO2013033016A1 DISTRIBUTED SUB-PAGE SELECTION 审中-公开
标题翻译：分页子选择
公开(公告)号：WO2013033016A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052516
申请日：2012-08-27
申请人： RAMBUS INC , VOGELSANG, Thomas
发明人： VOGELSANG, Thomas
IPC分类号： G11C11/4063 , G11C11/4091
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/08 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/4085 , G11C11/4094 , G11C11/4097
摘要： Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.
摘要翻译：描述了动态，随机存取存储器（DRAM）架构和用于将存储器激活细分为页面的分数的方法。支持子页面激活的电路放置在本地字线驱动器和读出放大器条纹的交叉点中，以允许对存储器单元的相邻阵列的独立控制，而没有显着的面积开销。

8. 发明申请

WO2013033628A1 TESTING THROUGH-SILICON-VIAS 审中-公开
标题翻译：通过硅玻璃测试
公开(公告)号：WO2013033628A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/053516
申请日：2012-08-31
申请人： RAMBUS INC. , VOGELSANG, Thomas , NG, William , WARE, Frederick, A.
发明人： VOGELSANG, Thomas , NG, William , WARE, Frederick, A.
IPC分类号： H01L23/58
CPC分类号： G11C29/04 , G01R31/2851 , G11C8/10 , G11C29/025 , H01L22/34 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/1434 , H01L2924/00
摘要： Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
摘要翻译：实施例通常涉及具有硅通孔（TSV）的集成电路器件。在一个实施例中，集成电路（IC）装置包括TSV的场和地址解码器，其将至少一个TSV可选地耦合到测试输入和测试评估电路中的至少一个。在另一实施例中，一种方法包括从至少一个IC器件中的TSV领域中选择一个或多个TSV，以及将每个选择的TS V耦合到测试输入和测试评估电路中的至少一个。

9. 发明申请

WO2012155115A1 STACKED DRAM DEVICE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：堆叠DRAM器件及其制造方法
公开(公告)号：WO2012155115A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/037664
申请日：2012-05-11
申请人： RAMBUS INC. , VOGELSANG, Thomas
发明人： VOGELSANG, Thomas
IPC分类号： H04L23/538 , G01C5/06
CPC分类号： G11C5/063 , G11C5/025 , H01L23/481 , H01L25/0657 , H01L27/10897 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers.
摘要翻译：存储器堆叠包括多个存储器管芯，其包括主管芯和一个或多个从属管芯。通过进一步处理可以将从属模具转换成主模具。从管芯包括具有存储单元阵列的存储器芯。从模具还包括分别在存储器芯中形成第一和第二配线的第一和第二金属层。从模具中的接口电路与第一和第二金属层分离。

10. 发明申请

WO2012074724A1 MEMORY REFRESH METHOD AND DEVICES 审中-公开
标题翻译：存储器刷新方法和器件
公开(公告)号：WO2012074724A1
公开(公告)日：2012-06-07
申请号：PCT/US2011/060458
申请日：2011-11-11
申请人： RAMBUS INC. , PEREGO, Richard , VOGELSANG, Thomas , BROOKS, John
发明人： PEREGO, Richard , VOGELSANG, Thomas , BROOKS, John
IPC分类号： G11C11/406 , G11C11/401 , G11C11/4063
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40618 , G11C11/408 , G11C2211/4061
摘要： The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an "opportunity" to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
摘要翻译：本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式